From 58092dc4dfde55d5824211e5aa1be47212a57f1f Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Mon, 19 Aug 2013 12:23:05 +0100 Subject: [PATCH] mfd: dbx500: Remove any mention of the BML8580CLK The platform which it pertains to is no longer supported and is actually causing some confusion in the new common clock implementation. A recent patch removed its use in the clock driver, let's take out the definitions too. Acked-by: Samuel Ortiz Signed-off-by: Lee Jones Signed-off-by: Linus Walleij --- drivers/mfd/db8500-prcmu.c | 1 - drivers/mfd/dbx500-prcmu-regs.h | 1 - include/dt-bindings/mfd/dbx500-prcmu.h | 27 +++++++++++++------------- 3 files changed, 13 insertions(+), 16 deletions(-) diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c index 53f371dcbb6e..b9ce60c301de 100644 --- a/drivers/mfd/db8500-prcmu.c +++ b/drivers/mfd/db8500-prcmu.c @@ -480,7 +480,6 @@ static struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = { CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true), CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true), CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true), - CLK_MGT_ENTRY(BML8580CLK, PLL_DIV, true), CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true), CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true), CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true), diff --git a/drivers/mfd/dbx500-prcmu-regs.h b/drivers/mfd/dbx500-prcmu-regs.h index 4f6f0fa5d3b7..7cc32a8ff01c 100644 --- a/drivers/mfd/dbx500-prcmu-regs.h +++ b/drivers/mfd/dbx500-prcmu-regs.h @@ -32,7 +32,6 @@ #define PRCM_PER7CLK_MGT (0x040) #define PRCM_LCDCLK_MGT (0x044) #define PRCM_BMLCLK_MGT (0x04C) -#define PRCM_BML8580CLK_MGT (0x108) #define PRCM_HSITXCLK_MGT (0x050) #define PRCM_HSIRXCLK_MGT (0x054) #define PRCM_HDMICLK_MGT (0x058) diff --git a/include/dt-bindings/mfd/dbx500-prcmu.h b/include/dt-bindings/mfd/dbx500-prcmu.h index b7ee8c909908..552a2d174f01 100644 --- a/include/dt-bindings/mfd/dbx500-prcmu.h +++ b/include/dt-bindings/mfd/dbx500-prcmu.h @@ -61,24 +61,23 @@ #define PRCMU_PLLSOC1 43 #define PRCMU_ARMSS 44 #define PRCMU_PLLDDR 45 -#define PRCMU_BML8580CLK 46 /* DSI Clocks */ -#define PRCMU_PLLDSI 47 -#define PRCMU_DSI0CLK 48 -#define PRCMU_DSI1CLK 49 -#define PRCMU_DSI0ESCCLK 50 -#define PRCMU_DSI1ESCCLK 51 -#define PRCMU_DSI2ESCCLK 52 +#define PRCMU_PLLDSI 46 +#define PRCMU_DSI0CLK 47 +#define PRCMU_DSI1CLK 48 +#define PRCMU_DSI0ESCCLK 49 +#define PRCMU_DSI1ESCCLK 50 +#define PRCMU_DSI2ESCCLK 51 /* LCD DSI PLL - Ux540 only */ -#define PRCMU_PLLDSI_LCD 53 -#define PRCMU_DSI0CLK_LCD 54 -#define PRCMU_DSI1CLK_LCD 55 -#define PRCMU_DSI0ESCCLK_LCD 56 -#define PRCMU_DSI1ESCCLK_LCD 57 -#define PRCMU_DSI2ESCCLK_LCD 58 +#define PRCMU_PLLDSI_LCD 52 +#define PRCMU_DSI0CLK_LCD 53 +#define PRCMU_DSI1CLK_LCD 54 +#define PRCMU_DSI0ESCCLK_LCD 55 +#define PRCMU_DSI1ESCCLK_LCD 56 +#define PRCMU_DSI2ESCCLK_LCD 57 -#define PRCMU_NUM_CLKS 59 +#define PRCMU_NUM_CLKS 58 #endif -- 2.39.5