From 590842f90984f96a3da6d8b59447dfa1d186d01e Mon Sep 17 00:00:00 2001 From: Matt Burtch Date: Mon, 17 Oct 2011 09:25:45 -0700 Subject: [PATCH] ARM: i.MX28: shift frac value in _CLK_SET_RATE Noticed when setting SSP0 in clk_set_rate, _CLK_SET_RATE attempts to reset the clock divider for the SSP0 parent clock, in this case IO0FRAC. Bits 24-29 of HW_CLKCTRL_FRAC0 are cleared correctly, but when the new frac value is written the value isn't shifted up to write the correct bit-field. This results in IO0FRAC being set to 0 and CPUFRAC being corrupted. This should occur when writing IO1FRAC, EMIFRAC in HW_CLKCTRL_FRAC0 and GPMIFRAC, HSADCFRAC in HW_CLKCTRL_FRAC1. Tested on custom i.MX28 board with SSP0 SPI driver. Signed-off-by: Matt Burtch Signed-off-by: Sascha Hauer --- arch/arm/mach-mxs/clock-mx28.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c index 5dcc59d5b9e..ba532279d1a 100644 --- a/arch/arm/mach-mxs/clock-mx28.c +++ b/arch/arm/mach-mxs/clock-mx28.c @@ -349,7 +349,7 @@ static int name##_set_rate(struct clk *clk, unsigned long rate) \ \ reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \ reg &= ~BM_CLKCTRL_##fr##_##fs##FRAC; \ - reg |= frac; \ + reg |= frac << BP_CLKCTRL_##fr##_##fs##FRAC; \ __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \ } \ \ -- 2.39.5