From 5abcd95d8c69008c72d54d7763e0ee2b5df84ac4 Mon Sep 17 00:00:00 2001 From: Boris Brezillon Date: Wed, 11 Nov 2015 22:30:30 +0100 Subject: [PATCH] mtd: nand: sunxi: adapt clk_rate to tWB, tADL, tWHR and tRHW timings Adapt the NAND controller clk rate to the tWB, tADL, tWHR and tRHW timings instead of returning an error when the maximum clk divisor is not big enough to provide an appropriate timing. Signed-off-by: Boris Brezillon --- drivers/mtd/nand/sunxi_nand.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/mtd/nand/sunxi_nand.c b/drivers/mtd/nand/sunxi_nand.c index b906fc5a22fe..e30276d9a9e3 100644 --- a/drivers/mtd/nand/sunxi_nand.c +++ b/drivers/mtd/nand/sunxi_nand.c @@ -1163,6 +1163,18 @@ static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip, min_clk_period = DIV_ROUND_UP(timings->tWC_min, 2); /* T16 - T19 + tCAD */ + if (timings->tWB_max > (min_clk_period * 20)) + min_clk_period = DIV_ROUND_UP(timings->tWB_max, 20); + + if (timings->tADL_min > (min_clk_period * 32)) + min_clk_period = DIV_ROUND_UP(timings->tADL_min, 32); + + if (timings->tWHR_min > (min_clk_period * 32)) + min_clk_period = DIV_ROUND_UP(timings->tWHR_min, 32); + + if (timings->tRHW_min > (min_clk_period * 20)) + min_clk_period = DIV_ROUND_UP(timings->tRHW_min, 20); + tWB = sunxi_nand_lookup_timing(tWB_lut, timings->tWB_max, min_clk_period); if (tWB < 0) { -- 2.39.5