From 5b851d465215533e1e6f66153f1bdf5bed7c6ff5 Mon Sep 17 00:00:00 2001 From: Ranjani Vaidyanathan Date: Wed, 11 May 2011 19:18:40 -0500 Subject: [PATCH] ENGR00143294-3: MX50-Port DVFS-CORE and bus_freq driver to 2.6.38 Port low power mode drivers to 2.6.38 Signed-off-by: Ranjani Vaidyanathan --- arch/arm/mach-mx5/board-mx50_rdp.c | 87 +++++++++++++++++++++-- arch/arm/mach-mx5/bus_freq.c | 9 +-- arch/arm/mach-mx5/devices-imx50.h | 7 ++ arch/arm/mach-mx5/mx50_rdp_pmic_mc13892.c | 29 ++++++-- arch/arm/plat-mxc/include/mach/mx50.h | 6 ++ 5 files changed, 121 insertions(+), 17 deletions(-) diff --git a/arch/arm/mach-mx5/board-mx50_rdp.c b/arch/arm/mach-mx5/board-mx50_rdp.c index 03b339b4b647..8a0acbc6f5d6 100755 --- a/arch/arm/mach-mx5/board-mx50_rdp.c +++ b/arch/arm/mach-mx5/board-mx50_rdp.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include @@ -42,6 +43,7 @@ #include "devices-imx50.h" #include "cpu_op-mx50.h" #include "devices.h" +#include "crm_regs.h" #define FEC_EN IMX_GPIO_NR(6, 23) #define FEC_RESET_B IMX_GPIO_NR(4, 12) @@ -83,6 +85,13 @@ #define MX50_RDP_EPDC_PMIC_WAKE IMX_GPIO_NR(6, 16) #define MX50_RDP_EPDC_PMIC_INT IMX_GPIO_NR(6, 17) #define MX50_RDP_EPDC_VCOM IMX_GPIO_NR(4, 21) +#define MX50_RDP_SD1_WP IMX_GPIO_NR(4, 19) /*GPIO_4_19 */ +#define MX50_RDP_SD1_CD IMX_GPIO_NR(1, 27) /*GPIO_1_27 */ +#define MX50_RDP_SD2_WP IMX_GPIO_NR(5, 16) /*GPIO_5_16 */ +#define MX50_RDP_SD2_CD IMX_GPIO_NR(5, 17) /*GPIO_5_17 */ +#define MX50_RDP_SD3_WP IMX_GPIO_NR(5, 28) /*GPIO_5_28 */ + +extern struct dvfs_op *(*get_dvfs_core_op)(int *wp); extern int mx50_rdp_init_mc13892(void); @@ -709,6 +718,70 @@ static struct gpmi_nfc_platform_data mx50_gpmi_nfc_platform_data __initdata = { .max_chip_count = 1, }; + +static struct mxc_dvfs_platform_data rdp_dvfscore_data = { + .reg_id = "cpu_vddgp", + .clk1_id = "cpu_clk", + .clk2_id = "gpc_dvfs_clk", + .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET, + .gpc_vcr_offset = MXC_GPC_VCR_OFFSET, + .ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET, + .ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET, + .ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET, + .prediv_mask = 0x1F800, + .prediv_offset = 11, + .prediv_val = 3, + .div3ck_mask = 0xE0000000, + .div3ck_offset = 29, + .div3ck_val = 2, + .emac_val = 0x08, + .upthr_val = 25, + .dnthr_val = 9, + .pncthr_val = 33, + .upcnt_val = 10, + .dncnt_val = 10, + .delay_time = 80, +}; + +static struct dvfs_op dvfs_core_setpoint[] = { + {33, 13, 33, 10, 10, 0x08}, /* 800MHz*/ + {28, 8, 33, 10, 10, 0x08}, /* 400MHz */ + {20, 0, 33, 20, 10, 0x08}, /* 160MHz*/ + {28, 8, 33, 20, 30, 0x08}, /*160MHz, AHB 133MHz, LPAPM mode*/ + {29, 0, 33, 20, 10, 0x08},}; /* 160MHz, AHB 24MHz */ + +static struct dvfs_op *mx50_rdp_get_dvfs_core_table(int *wp) +{ + *wp = ARRAY_SIZE(dvfs_core_setpoint); + return dvfs_core_setpoint; +} + +static struct mxc_bus_freq_platform_data rdp_bus_freq_data = { + .gp_reg_id = "cpu_vddgp", + .lp_reg_id = "lp_vcc", +}; + +static const struct esdhc_platform_data mx50_rdp_sd1_data __initconst = { + .cd_gpio = MX50_RDP_SD1_CD, + .wp_gpio = MX50_RDP_SD1_WP, +}; + +static const struct esdhc_platform_data mx50_rdp_sd2_data __initconst = { + .cd_gpio = MX50_RDP_SD2_CD, + .wp_gpio = MX50_RDP_SD2_WP, +}; + +static const struct esdhc_platform_data mx50_rdp_sd3_data __initconst = { + .wp_gpio = MX50_RDP_SD3_WP, + .always_present = 1, +}; + +static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, + char **cmdline, struct meminfo *mi) +{ + get_dvfs_core_op = mx50_rdp_get_dvfs_core_table; +} + /* * Board specific initialization. */ @@ -740,16 +813,19 @@ static void __init mx50_rdp_board_init(void) i2c_register_board_info(0, mxc_i2c0_board_info, ARRAY_SIZE(mxc_i2c0_board_info)); mxc_register_device(&max17135_sensor_device, NULL); - imx50_add_imx_epdc(&epdc_data); - imx50_add_mxc_gpu(&gpu_data); - imx50_add_sdhci_esdhc_imx(0, NULL); - imx50_add_sdhci_esdhc_imx(1, NULL); - imx50_add_sdhci_esdhc_imx(2, NULL); + imx50_add_imx_epdc(&epdc_data); + imx50_add_mxc_gpu(&gpu_data); + imx50_add_sdhci_esdhc_imx(0, &mx50_rdp_sd1_data); + imx50_add_sdhci_esdhc_imx(1, &mx50_rdp_sd2_data); + imx50_add_sdhci_esdhc_imx(2, &mx50_rdp_sd3_data); imx50_add_otp(); imx50_add_dcp(); imx50_add_rngb(); imx50_add_perfmon(); mx50_rdp_init_mc13892(); + + imx50_add_dvfs_core(&rdp_dvfscore_data); + imx50_add_busfreq(&rdp_bus_freq_data); } static void __init mx50_rdp_timer_init(void) @@ -762,6 +838,7 @@ static struct sys_timer mx50_rdp_timer = { }; MACHINE_START(MX50_RDP, "Freescale MX50 Reference Design Platform") + .fixup = fixup_mxc_board, .map_io = mx50_map_io, .init_early = imx50_init_early, .init_irq = mx50_init_irq, diff --git a/arch/arm/mach-mx5/bus_freq.c b/arch/arm/mach-mx5/bus_freq.c index 37e9038e37f1..fb0a0397ac9b 100755 --- a/arch/arm/mach-mx5/bus_freq.c +++ b/arch/arm/mach-mx5/bus_freq.c @@ -120,7 +120,6 @@ void exit_lpapm_mode_mx53(void); int low_freq_bus_used(void); void set_ddr_freq(int ddr_freq); -extern int dvfs_core_is_active; extern struct cpu_op *(*get_cpu_op)(int *op); extern void __iomem *ccm_base; extern void __iomem *databahn_base; @@ -128,12 +127,6 @@ extern int update_ddr_freq(int ddr_rate); extern unsigned int mx50_ddr_type; -struct dvfs_wp dvfs_core_setpoint[] = { - {33, 8, 33, 10, 10, 0x08}, - {26, 0, 33, 20, 10, 0x08}, - {28, 8, 33, 20, 30, 0x08}, - {29, 0, 33, 20, 10, 0x08},}; - static DEFINE_SPINLOCK(voltage_lock); struct mutex bus_freq_mutex; @@ -1023,7 +1016,7 @@ static int __devinit busfreq_probe(struct platform_device *pdev) static struct platform_driver busfreq_driver = { .driver = { - .name = "busfreq", + .name = "imx_busfreq", }, .probe = busfreq_probe, .suspend = busfreq_suspend, diff --git a/arch/arm/mach-mx5/devices-imx50.h b/arch/arm/mach-mx5/devices-imx50.h index 53a3e2520ebc..0cc376dcb7c5 100755 --- a/arch/arm/mach-mx5/devices-imx50.h +++ b/arch/arm/mach-mx5/devices-imx50.h @@ -81,3 +81,10 @@ extern const struct imx_spi_imx_data imx50_cspi_data[] __initconst; #define imx50_add_cspi(id, pdata) \ imx_add_spi_imx(&imx50_cspi_data[id], pdata) +extern const struct imx_dvfs_core_data imx50_dvfs_core_data __initconst; +#define imx50_add_dvfs_core(pdata) \ + imx_add_dvfs_core(&imx50_dvfs_core_data, pdata) + +#define imx50_add_busfreq(pdata) imx_add_busfreq(pdata) + + diff --git a/arch/arm/mach-mx5/mx50_rdp_pmic_mc13892.c b/arch/arm/mach-mx5/mx50_rdp_pmic_mc13892.c index 96cc65f70ba9..b594677207db 100644 --- a/arch/arm/mach-mx5/mx50_rdp_pmic_mc13892.c +++ b/arch/arm/mach-mx5/mx50_rdp_pmic_mc13892.c @@ -94,7 +94,13 @@ /* CPU */ static struct regulator_consumer_supply sw1_consumers[] = { { - .supply = "cpu_vcc", + .supply = "cpu_vddgp", + } +}; + +static struct regulator_consumer_supply sw2_consumers[] = { + { + .supply = "lp_vcc", } }; @@ -114,6 +120,15 @@ static struct regulator_consumer_supply vgen1_consumers[] = { }, }; +static struct regulator_consumer_supply vsd_consumers[] = { + REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.1"), +}; + +static struct regulator_consumer_supply vgen2_consumers[] = { + REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.0"), + REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.2"), +}; + static struct regulator_init_data sw1_init = { .constraints = { .name = "SW1", @@ -146,7 +161,9 @@ static struct regulator_init_data sw2_init = { .mode = REGULATOR_MODE_NORMAL, .enabled = 1, }, - } + }, + .num_consumer_supplies = ARRAY_SIZE(sw2_consumers), + .consumer_supplies = sw2_consumers, }; static struct regulator_init_data sw3_init = { @@ -267,7 +284,9 @@ static struct regulator_init_data vsd_init = { .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, .always_on = 1, - } + }, + .num_consumer_supplies = ARRAY_SIZE(vsd_consumers), + .consumer_supplies = vsd_consumers, }; static struct regulator_init_data vcam_init = { @@ -302,7 +321,9 @@ static struct regulator_init_data vgen2_init = { .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, .always_on = 1, - } + }, + .num_consumer_supplies = ARRAY_SIZE(vgen2_consumers), + .consumer_supplies = vgen2_consumers, }; static struct regulator_init_data vgen3_init = { diff --git a/arch/arm/plat-mxc/include/mach/mx50.h b/arch/arm/plat-mxc/include/mach/mx50.h index 8d4c2dde84b6..ec37ab16f6e8 100755 --- a/arch/arm/plat-mxc/include/mach/mx50.h +++ b/arch/arm/plat-mxc/include/mach/mx50.h @@ -143,6 +143,12 @@ #define MX50_MSHC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f4000) #define MX50_RNGB_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f8000) +#define MX50_DVFSCORE_BASE_ADDR (MX50_GPC_BASE_ADDR + 0x180) + +/* GPC offsets */ +#define MXC_GPC_CNTR_OFFSET 0x0 +#define MXC_GPC_PGR_OFFSET 0x4 +#define MXC_GPC_VCR_OFFSET 0x8 /* * AIPS 2 -- 2.39.2