From 61cf7d6fb9a2da3d1746acffc301fda7120632a0 Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Fri, 20 Apr 2012 14:37:56 +0800 Subject: [PATCH] ENGR00180412 MX6 SATA: Enable PHY in the SATA initilization iENGR00179574: MX6- Add bus frequency scaling support disable SATA PHY defaultly Enable PHY in the SATA initilization, make sure the SATA work well. Signed-off-by: Richard Zhu --- arch/arm/plat-mxc/ahci_sata.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/arm/plat-mxc/ahci_sata.c b/arch/arm/plat-mxc/ahci_sata.c index 0d78a123a469..cee34b6f70d9 100644 --- a/arch/arm/plat-mxc/ahci_sata.c +++ b/arch/arm/plat-mxc/ahci_sata.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -18,11 +18,13 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. */ +#include #include #include #include #include -#include + +#include #include int write_phy_ctl_ack_polling(u32 data, void __iomem *mmio, @@ -140,6 +142,13 @@ int sata_init(void __iomem *addr, unsigned long timer1ms) u32 tmpdata; int iterations = 20; + /* + * Make sure that SATA PHY is enabled + * The PDDQ mode is disabled. + */ + tmpdata = readl(addr + PORT_PHY_CTL); + writel(tmpdata & (~PORT_PHY_CTL_PDDQ_LOC), addr + PORT_PHY_CTL); + /* Reset HBA */ writel(HOST_RESET, addr + HOST_CTL); -- 2.39.5