From 679e8ff32175d7756fdacaeed3e594024f6e8de2 Mon Sep 17 00:00:00 2001 From: Danny Nold Date: Mon, 2 May 2011 12:35:05 -0500 Subject: [PATCH] ENGR00142954 - MSL clocks: correct APLL settings to prevent random PxP lockups - Add appropriate bit settings to ANADIG_MISC to improve APLL signal integrity and prevent intermittent PxP lockups Signed-off-by: Danny Nold --- arch/arm/mach-mx5/clock_mx50.c | 14 ++++++++++++-- arch/arm/mach-mx5/crm_regs.h | 4 ++++ 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-mx5/clock_mx50.c b/arch/arm/mach-mx5/clock_mx50.c index ff3b0eb0f771..446e1e2ff476 100755 --- a/arch/arm/mach-mx5/clock_mx50.c +++ b/arch/arm/mach-mx5/clock_mx50.c @@ -324,18 +324,28 @@ static struct clk ckil_clk = { static int apll_enable(struct clk *clk) { - __raw_writel(1, apll_base + MXC_ANADIG_MISC_SET); + /* Set bit to flush multiple edges out of PLL vco */ + __raw_writel(MXC_ANADIG_PLL_HOLD_RING_OFF, + apll_base + MXC_ANADIG_MISC_SET); + + __raw_writel(MXC_ANADIG_PLL_POWERUP, apll_base + MXC_ANADIG_MISC_SET); if (!WAIT(__raw_readl(apll_base + MXC_ANADIG_PLLCTRL) & MXC_ANADIG_APLL_LOCK, 80000)) panic("apll_enable failed!\n"); + /* Clear after relocking, then wait 10 us */ + __raw_writel(MXC_ANADIG_PLL_HOLD_RING_OFF, + apll_base + MXC_ANADIG_MISC_CLR); + + udelay(10); + return 0; } static void apll_disable(struct clk *clk) { - __raw_writel(1, apll_base + MXC_ANADIG_MISC_CLR); + __raw_writel(MXC_ANADIG_PLL_POWERUP, apll_base + MXC_ANADIG_MISC_CLR); } static unsigned long apll_get_rate(struct clk *clk) diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h index 864cca86ba23..c32d19f6ddb9 100755 --- a/arch/arm/mach-mx5/crm_regs.h +++ b/arch/arm/mach-mx5/crm_regs.h @@ -125,6 +125,10 @@ #define MXC_ANADIG_PFD4_STABLE (1 << 6) #define MXC_ANADIG_PFD4_FRAC_OFFSET 0 +#define MXC_ANADIG_REF_SELFBIAS_OFF (1 << 20) +#define MXC_ANADIG_PLL_HOLD_RING_OFF (1 << 7) +#define MXC_ANADIG_PLL_POWERUP (1 << 0) + #define MXC_ANADIG_APLL_LOCK (1 << 31) #define MXC_ANADIG_APLL_FORCE_LOCK (1 << 30) #define MXC_ANADIG_PFD_DIS_OFFSET 16 -- 2.39.5