From 75d77e72e45e43ea01fc9ee02763e6a5b833e68e Mon Sep 17 00:00:00 2001 From: Guenter Roeck Date: Tue, 9 Oct 2012 12:27:12 -0700 Subject: [PATCH] hwmon: (coretemp) Drop dependency on PCI for TjMax detection on Atom CPUs So far, we use the NM10 Express Chipset PCI chip ID to detect TjMax for Atom CPUs with model 0x1c. As it turns out, we can use the CPU stepping (x86_mask) for the same purpose; stepping is 10 for all model 0x1c CPUs with TjMax of 100 degrees C. This was verified by checking the output of /proc/cpuinfo for the respective CPUs (D4xx, D5xx, N4xx, N5xx). Other CPUs currently covered by the same code (Exx, Z6xx, Z2460) are not supported by the NM10 Express Chipset. Most of those CPUs have TjMax of 90 degrees C, except for E6xxT models which have a TjMax of 110 degrees C. E6xxT CPUs can however not be detected by software. Calculate TjMax for Atom CPUs as follows. Note that the listed values are not correct in some cases (230, 330). tjmax_table is used for those to override the default values. ID Stepping TjMax Models 0x1c 10 100 D4xx, N4xx, D5xx, N5xx 0x1c not 10 90 Z5xx, N2xx, 230, 330, others 0x26 - 90 Atom Tunnel Creek (Exx), Lincroft (Z6xx) 0x27 - 90 Atom Medfield (Z2460) 0x36 - 100 Atom Cedar Trail (N2xxx, D2xxx) Also drop the module dependency on PCI. Signed-off-by: Guenter Roeck Acked-by: Jean Delvare --- drivers/hwmon/Kconfig | 2 +- drivers/hwmon/coretemp.c | 37 +++++++++++++++---------------------- 2 files changed, 16 insertions(+), 23 deletions(-) diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index 9e3d977c106b..42f21ad56276 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -455,7 +455,7 @@ config SENSORS_HIH6130 config SENSORS_CORETEMP tristate "Intel Core/Core2/Atom temperature sensor" - depends on X86 && PCI + depends on X86 help If you say yes here you get support for the temperature sensor inside your CPU. Most of the family 6 CPUs diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c index 47b8d84b489d..1653d0ddd1d0 100644 --- a/drivers/hwmon/coretemp.c +++ b/drivers/hwmon/coretemp.c @@ -34,7 +34,6 @@ #include #include #include -#include #include #include #include @@ -222,7 +221,6 @@ static int __cpuinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id, int usemsr_ee = 1; int err; u32 eax, edx; - struct pci_dev *host_bridge; int i; /* explicit tjmax table entries override heuristics */ @@ -231,31 +229,26 @@ static int __cpuinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id, return tjmax_table[i].tjmax; } - /* Early chips have no MSR for TjMax */ - - if (c->x86_model == 0xf && c->x86_mask < 4) - usemsr_ee = 0; - /* Atom CPUs */ - if (c->x86_model == 0x1c || c->x86_model == 0x26 - || c->x86_model == 0x27) { - usemsr_ee = 0; - - host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); + if (c->x86_model == 0x1c) { + /* + * TjMax for stepping 10 CPUs (N4xx, N5xx, D4xx, D5xx) + * is 100 degrees C, for all others it is 90 degrees C. + */ + if (c->x86_mask == 10) + return 100000; + return 90000; + } else if (c->x86_model == 0x26 || c->x86_model == 0x27) { + return 90000; + } else if (c->x86_model == 0x36) { + return 100000; + } - if (host_bridge && host_bridge->vendor == PCI_VENDOR_ID_INTEL - && (host_bridge->device == 0xa000 /* NM10 based nettop */ - || host_bridge->device == 0xa010)) /* NM10 based netbook */ - tjmax = 100000; - else - tjmax = 90000; + /* Early chips have no MSR for TjMax */ - pci_dev_put(host_bridge); - } else if (c->x86_model == 0x36) { + if (c->x86_model == 0xf && c->x86_mask < 4) usemsr_ee = 0; - tjmax = 100000; - } if (c->x86_model > 0xe && usemsr_ee) { u8 platform_id; -- 2.39.5