From 7632f648d7b4fc68e06c730d4dbd2e95dd54da59 Mon Sep 17 00:00:00 2001 From: Zeng Zhaoming Date: Wed, 6 Apr 2011 04:47:32 +0800 Subject: [PATCH] ENGR00141651-1 MX53,Loco: audio not work when ipmux2 clock disabled in idle When SOC enter wait mode, ipmux2_clk will disable to save power, if using ssi1 for audio transfer, audio will not work correctly. To around this, using ssi2. Signed-off-by: Zeng Zhaoming --- arch/arm/mach-mx5/board-mx53_evk.c | 636 +++++++++++++++++++++++++++- arch/arm/mach-mx5/board-mx53_loco.c | 449 +++++++++++++++++++- arch/arm/mach-mx5/board-mx53_smd.c | 387 ++++++++++++++++- 3 files changed, 1454 insertions(+), 18 deletions(-) mode change 100644 => 100755 arch/arm/mach-mx5/board-mx53_evk.c mode change 100644 => 100755 arch/arm/mach-mx5/board-mx53_loco.c mode change 100644 => 100755 arch/arm/mach-mx5/board-mx53_smd.c diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c old mode 100644 new mode 100755 index f87d571882c6..3dfab9f7473c --- a/arch/arm/mach-mx5/board-mx53_evk.c +++ b/arch/arm/mach-mx5/board-mx53_evk.c @@ -21,25 +21,103 @@ #include #include +#include #include #include #include #include +#include +#include +#include + #include #include #include #include #include +#include #include - -#define MX53_EVK_FEC_PHY_RST IMX_GPIO_NR(7, 6) -#define EVK_ECSPI1_CS0 IMX_GPIO_NR(2, 30) -#define EVK_ECSPI1_CS1 IMX_GPIO_NR(3, 19) +#include +#include #include "crm_regs.h" #include "devices-imx53.h" +#include "devices.h" + +#define MX53_EVK_FEC_PHY_RST IMX_GPIO_NR(7, 6) +#define EVK_ECSPI1_CS0 IMX_GPIO_NR(2, 30) +#define EVK_ECSPI1_CS1 IMX_GPIO_NR(3, 19) +#define EVK_HP_DETECT IMX_GPIO_NR(2, 5) /* GPIO_2_5 */ +#define EVK_ECSPI1_CS0 IMX_GPIO_NR(2, 30) +#define EVK_SD3_CD IMX_GPIO_NR(3, 11) /* GPIO_3_11 */ +#define EVK_SD3_WP IMX_GPIO_NR(3, 12) /* GPIO_3_12 */ +#define EVK_SD1_CD IMX_GPIO_NR(3, 13) /* GPIO_3_13 */ +#define EVK_SD1_WP IMX_GPIO_NR(3, 14) /* GPIO_3_14 */ +#define EVK_ECSPI1_CS1 IMX_GPIO_NR(3, 19) +#define EVK_DISP0_PD IMX_GPIO_NR(3, 24) /* GPIO_3_24 */ +#define EVK_TS_INT IMX_GPIO_NR(3, 26) /* GPIO_3_26 */ +#define EVK_DISP0_I2C_EN IMX_GPIO_NR(3, 28) /* GPIO_3_28 */ +#define EVK_DISP0_DET_INT IMX_GPIO_NR(3, 31) /* GPIO_3_31 */ +#define EVK_CAM_RESET IMX_GPIO_NR(4, 0) /* GPIO_4_0 */ +#define EVK_ESAI_RESET IMX_GPIO_NR(4, 2) /* GPIO_4_2 */ +#define EVK_CAN2_EN2 IMX_GPIO_NR(4, 4) /* GPIO_4_4 */ +#define EVK_12V_EN IMX_GPIO_NR(4, 5) /* GPIO_4_5 */ +#define EVK_DISP0_RESET IMX_GPIO_NR(5, 0) /* GPIO_5_0 */ +#define EVK_USB_HUB_RESET IMX_GPIO_NR(5, 20) /* GPIO_5_20 */ +#define EVK_TVIN_PWR IMX_GPIO_NR(5, 23) /* GPIO_5_23 */ +#define EVK_CAN2_EN1 IMX_GPIO_NR(5, 24) /* GPIO_5_24 */ +#define EVK_TVIN_RESET IMX_GPIO_NR(5, 25) /* GPIO_5_25 */ +#define EVK_OTG_VBUS IMX_GPIO_NR(6, 6) /* GPIO_6_6 */ +#define EVK_FEC_PHY_RST IMX_GPIO_NR(7, 6) +#define EVK_USBH1_VBUS IMX_GPIO_NR(7, 8) /* GPIO_7_8 */ +#define EVK_PMIC_INT IMX_GPIO_NR(7, 11) /* GPIO_7_11 */ +#define EVK_CAN1_EN1 IMX_GPIO_NR(7, 12) /* GPIO_7_12 */ +#define EVK_CAN1_EN2 IMX_GPIO_NR(7, 13) /* GPIO_7_13 */ + +#define ARM2_SD1_CD IMX_GPIO_NR(1, 1) /* GPIO_1_1 */ +#define ARM2_OTG_VBUS IMX_GPIO_NR(3, 22) /* GPIO_3_22 */ +#define ARM2_LCD_CONTRAST IMX_GPIO_NR(4, 20) /* GPIO_4_20 */ + +static iomux_v3_cfg_t mx53common_pads[] = { + MX53_PAD_EIM_WAIT__GPIO5_0, + + MX53_PAD_EIM_OE__IPU_DI1_PIN7, + MX53_PAD_EIM_RW__IPU_DI1_PIN8, + + MX53_PAD_EIM_A25__IPU_DI0_D1_CS, + + MX53_PAD_EIM_D16__ECSPI1_SCLK, + MX53_PAD_EIM_D17__ECSPI1_MISO, + MX53_PAD_EIM_D18__ECSPI1_MOSI, + + MX53_PAD_EIM_D20__IPU_SER_DISP0_CS, + + MX53_PAD_EIM_D23__IPU_DI0_D0_CS, + + MX53_PAD_EIM_D24__GPIO3_24, + MX53_PAD_EIM_D26__GPIO3_26, + + MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS, + + MX53_PAD_EIM_D30__IPU_DI0_PIN11, + MX53_PAD_EIM_D31__IPU_DI0_PIN12, + + MX53_PAD_PATA_DA_1__GPIO7_7, + MX53_PAD_PATA_DATA4__GPIO2_4, + MX53_PAD_PATA_DATA5__GPIO2_5, + MX53_PAD_PATA_DATA6__GPIO2_6, + + MX53_PAD_SD2_CLK__ESDHC2_CLK, + MX53_PAD_SD2_CMD__ESDHC2_CMD, + MX53_PAD_SD2_DATA0__ESDHC2_DAT0, + MX53_PAD_SD2_DATA1__ESDHC2_DAT1, + MX53_PAD_SD2_DATA2__ESDHC2_DAT2, + MX53_PAD_SD2_DATA3__ESDHC2_DAT3, + MX53_PAD_PATA_DATA12__ESDHC2_DAT4, + MX53_PAD_PATA_DATA13__ESDHC2_DAT5, + MX53_PAD_PATA_DATA14__ESDHC2_DAT6, + MX53_PAD_PATA_DATA15__ESDHC2_DAT7, -static iomux_v3_cfg_t mx53_evk_pads[] = { MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, @@ -51,19 +129,295 @@ static iomux_v3_cfg_t mx53_evk_pads[] = { MX53_PAD_PATA_CS_0__UART3_TXD_MUX, MX53_PAD_PATA_CS_1__UART3_RXD_MUX, - MX53_PAD_EIM_D16__ECSPI1_SCLK, - MX53_PAD_EIM_D17__ECSPI1_MISO, - MX53_PAD_EIM_D18__ECSPI1_MOSI, + MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC, + MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD, + MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS, + MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD, + + MX53_PAD_CSI0_DAT7__GPIO5_25, + + MX53_PAD_GPIO_2__MLB_MLBDAT, + MX53_PAD_GPIO_3__MLB_MLBCLK, + + MX53_PAD_GPIO_6__MLB_MLBSIG, + + MX53_PAD_GPIO_4__GPIO1_4, + MX53_PAD_GPIO_7__GPIO1_7, + MX53_PAD_GPIO_8__GPIO1_8, + + MX53_PAD_GPIO_10__GPIO4_0, + + MX53_PAD_KEY_COL2__CAN1_TXCAN, + MX53_PAD_KEY_ROW2__CAN1_RXCAN, + + /* CAN1 -- EN */ + MX53_PAD_GPIO_18__GPIO7_13, + /* CAN1 -- STBY */ + MX53_PAD_GPIO_17__GPIO7_12, + /* CAN1 -- NERR */ + MX53_PAD_GPIO_5__GPIO1_5, + + MX53_PAD_KEY_COL4__CAN2_TXCAN, + MX53_PAD_KEY_ROW4__CAN2_RXCAN, + + /* CAN2 -- EN */ + MX53_PAD_CSI0_DAT6__GPIO5_24, + /* CAN2 -- STBY */ + MX53_PAD_GPIO_14__GPIO4_4, + /* CAN2 -- NERR */ + MX53_PAD_CSI0_DAT4__GPIO5_22, + + MX53_PAD_GPIO_11__GPIO4_1, + MX53_PAD_GPIO_12__GPIO4_2, + MX53_PAD_GPIO_13__GPIO4_3, + MX53_PAD_GPIO_16__GPIO7_11, + MX53_PAD_GPIO_19__GPIO4_5, + + /* DI0 display clock */ + MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK, + + /* DI0 data enable */ + MX53_PAD_DI0_PIN15__IPU_DI0_PIN15, + /* DI0 HSYNC */ + MX53_PAD_DI0_PIN2__IPU_DI0_PIN2, + /* DI0 VSYNC */ + MX53_PAD_DI0_PIN3__IPU_DI0_PIN3, + + MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0, + MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1, + MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2, + MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3, + MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4, + MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5, + MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6, + MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7, + MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8, + MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9, + MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10, + MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11, + MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12, + MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13, + MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14, + MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15, + MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16, + MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17, + MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18, + MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19, + MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20, + MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21, + MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22, + MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23, + + MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3, + MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK, + MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2, + MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1, + MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0, + + MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3, + MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK, + MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2, + MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1, + MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0, + + /* audio and CSI clock out */ + MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK, + + MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12, + MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13, + MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14, + MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15, + MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16, + MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17, + MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18, + MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19, - /* ecspi chip select lines */ - MX53_PAD_EIM_EB2__GPIO2_30, - MX53_PAD_EIM_D19__GPIO3_19, + MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC, + MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC, + MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK, + /* Camera low power */ + MX53_PAD_CSI0_DAT5__GPIO5_23, + + /* esdhc1 */ + MX53_PAD_SD1_CMD__ESDHC1_CMD, + MX53_PAD_SD1_CLK__ESDHC1_CLK, + MX53_PAD_SD1_DATA0__ESDHC1_DAT0, + MX53_PAD_SD1_DATA1__ESDHC1_DAT1, + MX53_PAD_SD1_DATA2__ESDHC1_DAT2, + MX53_PAD_SD1_DATA3__ESDHC1_DAT3, + + /* esdhc3 */ + MX53_PAD_PATA_DATA8__ESDHC3_DAT0, + MX53_PAD_PATA_DATA9__ESDHC3_DAT1, + MX53_PAD_PATA_DATA10__ESDHC3_DAT2, + MX53_PAD_PATA_DATA11__ESDHC3_DAT3, + MX53_PAD_PATA_DATA0__ESDHC3_DAT4, + MX53_PAD_PATA_DATA1__ESDHC3_DAT5, + MX53_PAD_PATA_DATA2__ESDHC3_DAT6, + MX53_PAD_PATA_DATA3__ESDHC3_DAT7, + MX53_PAD_PATA_RESET_B__ESDHC3_CMD, + MX53_PAD_PATA_IORDY__ESDHC3_CLK, + + /* FEC pins */ + MX53_PAD_FEC_MDIO__FEC_MDIO, + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK, + MX53_PAD_FEC_RX_ER__FEC_RX_ER, + MX53_PAD_FEC_CRS_DV__FEC_RX_DV, + MX53_PAD_FEC_RXD1__FEC_RDATA_1, + MX53_PAD_FEC_RXD0__FEC_RDATA_0, + MX53_PAD_FEC_TX_EN__FEC_TX_EN, + MX53_PAD_FEC_TXD1__FEC_TDATA_1, + MX53_PAD_FEC_TXD0__FEC_TDATA_0, + MX53_PAD_FEC_MDC__FEC_MDC, + + MX53_PAD_CSI0_DAT8__I2C1_SDA, + MX53_PAD_CSI0_DAT9__I2C1_SCL, + + MX53_PAD_KEY_COL3__I2C2_SCL, + MX53_PAD_KEY_ROW3__I2C2_SDA, +}; + +static iomux_v3_cfg_t mx53evk_pads[] = { + /* USB OTG USB_OC */ + MX53_PAD_EIM_A24__GPIO5_4, + + /* USB OTG USB_PWR */ + MX53_PAD_EIM_A23__GPIO6_6, + + /* DISPB0_SER_CLK */ + MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK, + + /* DI0_PIN1 */ + MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN, + + /* DISP0 I2C ENABLE */ + MX53_PAD_EIM_D28__GPIO3_28, + + /* DISP0 DET */ + MX53_PAD_EIM_D31__GPIO3_31, + + /* SDHC1 SD_CD */ + MX53_PAD_EIM_DA13__GPIO3_13, + + /* SDHC1 SD_WP */ + MX53_PAD_EIM_DA14__GPIO3_14, + + /* SDHC3 SD_CD */ + MX53_PAD_EIM_DA11__GPIO3_11, + + /* SDHC3 SD_WP */ + MX53_PAD_EIM_DA12__GPIO3_12, + + /* PWM backlight */ + MX53_PAD_GPIO_1__PWM2_PWMO, + + /* USB HOST USB_PWR */ + MX53_PAD_PATA_DA_2__GPIO7_8, + + /* USB HOST USB_RST */ + MX53_PAD_CSI0_DATA_EN__GPIO5_20, + + /* USB HOST CARD_ON */ + MX53_PAD_EIM_DA15__GPIO3_15, + + /* USB HOST CARD_RST */ + MX53_PAD_PATA_DATA7__GPIO2_7, + + /* USB HOST WAN_WAKE */ + MX53_PAD_EIM_D25__GPIO3_25, + + /* FEC_RST */ + MX53_PAD_PATA_DA_0__GPIO7_6, +}; + +static iomux_v3_cfg_t mx53arm2_pads[] = { + /* USB OTG USB_OC */ + MX53_PAD_EIM_D21__GPIO3_21, + + /* USB OTG USB_PWR */ + MX53_PAD_EIM_D22__GPIO3_22, + + /* SDHC1 SD_CD */ + MX53_PAD_GPIO_1__GPIO1_1, + + /* gpio backlight */ + MX53_PAD_DI0_PIN4__GPIO4_20, +}; + +static iomux_v3_cfg_t mx53_nand_pads[] = { + MX53_PAD_NANDF_CLE__EMI_NANDF_CLE, + MX53_PAD_NANDF_ALE__EMI_NANDF_ALE, + MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B, + MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B, + MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B, + MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0, + MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0, + MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 , + MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2, + MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 , + MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0, + MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1, + MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2, + MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3, + MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4, + MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5, + MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6, + MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7, }; static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; +static struct fb_videomode video_modes[] = { + { + /* 800x480 @ 57 Hz , pixel clk @ 27MHz */ + "CLAA-WVGA", 57, 800, 480, 37037, 40, 60, 10, 10, 20, 10, + FB_SYNC_CLK_LAT_FALL, + FB_VMODE_NONINTERLACED, + 0,}, + { + /* 1600x1200 @ 60 Hz 162M pixel clk*/ + "UXGA", 60, 1600, 1200, 6172, + 304, 64, + 1, 46, + 192, 3, + FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, + FB_VMODE_NONINTERLACED, + 0,}, +}; + +static struct ipuv3_fb_platform_data loco_fb_di0_data = { + .interface_pix_fmt = IPU_PIX_FMT_RGB565, + .mode_str = "CLAA-WVGA", + .modes = video_modes, + .num_modes = ARRAY_SIZE(video_modes), +}; + +static struct ipuv3_fb_platform_data loco_fb_di1_data = { + .interface_pix_fmt = IPU_PIX_FMT_GBR24, + .mode_str = "1024x768M-16@60", + .modes = video_modes, + .num_modes = ARRAY_SIZE(video_modes), +}; + +static struct imx_ipuv3_platform_data ipu_data = { + .rev = 3, + .fb_head0_platform_data = &loco_fb_di0_data, + .fb_head1_platform_data = &loco_fb_di1_data, +}; + +static struct platform_pwm_backlight_data evk_pwm_backlight_data = { + .pwm_id = 1, + .max_brightness = 255, + .dft_brightness = 128, + .pwm_period_ns = 50000, +}; + +static struct fsl_mxc_tve_platform_data tve_data = { + .dac_reg = "VVIDEO", +}; + static inline void mx53_evk_init_uart(void) { imx53_add_imx_uart(0, NULL); @@ -115,16 +469,272 @@ static const struct spi_imx_master mx53_evk_spi_data __initconst = { .num_chipselect = ARRAY_SIZE(mx53_evk_spi_cs), }; +static struct i2c_board_info mxc_i2c0_board_info[] __initdata = { +}; + +static void sii902x_hdmi_reset(void) +{ + gpio_set_value(EVK_DISP0_RESET, 0); + msleep(10); + gpio_set_value(EVK_DISP0_RESET, 1); + msleep(10); +} + +static struct fsl_mxc_lcd_platform_data sii902x_hdmi_data = { + .reset = sii902x_hdmi_reset, +}; + +static void ddc_dvi_init(void) +{ + /* enable DVI I2C */ + gpio_set_value(EVK_DISP0_I2C_EN, 1); +} + +static int ddc_dvi_update(void) +{ + /* DVI cable state */ + if (gpio_get_value(EVK_DISP0_DET_INT) == 1) + return 1; + else + return 0; +} + +static struct fsl_mxc_ddc_platform_data evk_ddc_dvi_data = { + .di = 0, + .init = ddc_dvi_init, + .update = ddc_dvi_update, + .analog_regulator = "VSD", +}; + +/* TO DO add platform data */ +static struct i2c_board_info mxc_i2c1_board_info[] __initdata = { + { + .type = "sgtl5000-i2c", + .addr = 0x0a, + }, + { + .type = "tsc2007", + .addr = 0x48, + .irq = gpio_to_irq(EVK_TS_INT), + }, + { + .type = "backlight-i2c", + .addr = 0x2c, + }, + { + .type = "mxc_ddc", + .addr = 0x50, + .irq = gpio_to_irq(EVK_DISP0_DET_INT), + .platform_data = &evk_ddc_dvi_data, + }, + { + .type = "sii902x", + .addr = 0x39, + .irq = gpio_to_irq(EVK_DISP0_DET_INT), + .platform_data = &sii902x_hdmi_data, + }, +}; + +static struct mxc_dvfs_platform_data evk_dvfs_core_data = { + .reg_id = "SW1", + .clk1_id = "cpu_clk", + .clk2_id = "gpc_dvfs_clk", + .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET, + .gpc_vcr_offset = MXC_GPC_VCR_OFFSET, + .ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET, + .ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET, + .ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET, + .prediv_mask = 0x1F800, + .prediv_offset = 11, + .prediv_val = 3, + .div3ck_mask = 0xE0000000, + .div3ck_offset = 29, + .div3ck_val = 2, + .emac_val = 0x08, + .upthr_val = 25, + .dnthr_val = 9, + .pncthr_val = 33, + .upcnt_val = 10, + .dncnt_val = 10, + .delay_time = 30, +}; + +static struct mxc_bus_freq_platform_data evk_bus_freq_data = { + .gp_reg_id = "SW1", + .lp_reg_id = "SW2", +}; + +static int __initdata enable_spdif = { 0 }; +static int __init spdif_setup(char *__unused) +{ + enable_spdif = 1; + return 1; +} +__setup("spdif", spdif_setup); + +static void __init mx53_evk_io_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(mx53common_pads, + ARRAY_SIZE(mx53common_pads)); + + if (board_is_mx53_arm2()) { + /* MX53 ARM2 CPU board */ + pr_info("MX53 ARM2 board \n"); + mxc_iomux_v3_setup_multiple_pads(mx53arm2_pads, + ARRAY_SIZE(mx53arm2_pads)); + + /* Config GPIO for OTG VBus */ + gpio_request(ARM2_OTG_VBUS, "otg-vbus"); + gpio_direction_output(ARM2_OTG_VBUS, 1); + + gpio_request(ARM2_SD1_CD, "sdhc1-cd"); + gpio_direction_input(ARM2_SD1_CD); /* SD1 CD */ + + gpio_request(ARM2_LCD_CONTRAST, "lcd-contrast"); + gpio_direction_output(ARM2_LCD_CONTRAST, 1); + } else { + /* MX53 EVK board */ + pr_info("MX53 EVK board \n"); + mxc_iomux_v3_setup_multiple_pads(mx53evk_pads, + ARRAY_SIZE(mx53evk_pads)); + + /* Host1 Vbus with GPIO high */ + gpio_request(EVK_USBH1_VBUS, "usbh1-vbus"); + gpio_direction_output(EVK_USBH1_VBUS, 1); + /* shutdown the Host1 Vbus when system bring up, + * Vbus will be opened in Host1 driver's probe function */ + gpio_set_value(EVK_USBH1_VBUS, 0); + + /* USB HUB RESET - De-assert USB HUB RESET_N */ + gpio_request(EVK_USB_HUB_RESET, "usb-hub-reset"); + gpio_direction_output(EVK_USB_HUB_RESET, 0); + msleep(1); + gpio_set_value(EVK_USB_HUB_RESET, 1); + + /* Config GPIO for OTG VBus */ + gpio_request(EVK_OTG_VBUS, "otg-vbus"); + gpio_direction_output(EVK_OTG_VBUS, 0); + if (board_is_mx53_evk_a()) /*rev A,"1" disable, "0" enable vbus*/ + gpio_set_value(EVK_OTG_VBUS, 1); + else if (board_is_mx53_evk_b()) /* rev B,"0" disable,"1" enable Vbus*/ + gpio_set_value(EVK_OTG_VBUS, 0); + + gpio_request(EVK_SD1_CD, "sdhc1-cd"); + gpio_direction_input(EVK_SD1_CD); /* SD1 CD */ + gpio_request(EVK_SD1_WP, "sdhc1-wp"); + gpio_direction_input(EVK_SD1_WP); /* SD1 WP */ + + /* SD3 CD */ + gpio_request(EVK_SD3_CD, "sdhc3-cd"); + gpio_direction_input(EVK_SD3_CD); + + /* SD3 WP */ + gpio_request(EVK_SD3_WP, "sdhc3-wp"); + gpio_direction_input(EVK_SD3_WP); + + /* reset FEC PHY */ + gpio_request(EVK_FEC_PHY_RST, "fec-phy-reset"); + gpio_direction_output(EVK_FEC_PHY_RST, 0); + msleep(1); + gpio_set_value(EVK_FEC_PHY_RST, 1); + + gpio_request(EVK_ESAI_RESET, "fesai-reset"); + gpio_direction_output(EVK_ESAI_RESET, 0); + } + + /* DISP0 Detect */ + gpio_request(EVK_DISP0_DET_INT, "disp0-detect"); + gpio_direction_input(EVK_DISP0_DET_INT); + /* DISP0 Reset - Assert for i2c disabled mode */ + gpio_request(EVK_DISP0_RESET, "disp0-reset"); + gpio_direction_output(EVK_DISP0_RESET, 0); + + /* DISP0 Power-down */ + gpio_request(EVK_DISP0_PD, "disp0-pd"); + gpio_direction_output(EVK_DISP0_PD, 1); + + /* DISP0 I2C enable */ + gpio_request(EVK_DISP0_I2C_EN, "disp0-i2c"); + gpio_direction_output(EVK_DISP0_I2C_EN, 0); + + mxc_iomux_v3_setup_multiple_pads(mx53_nand_pads, + ARRAY_SIZE(mx53_nand_pads)); + + gpio_request(EVK_PMIC_INT, "pmic-int"); + gpio_direction_input(EVK_PMIC_INT); /*PMIC_INT*/ + + /* headphone_det_b */ + gpio_request(EVK_HP_DETECT, "hp-detect"); + gpio_direction_input(EVK_HP_DETECT); + + /* power key */ + + /* LCD related gpio */ + + /* Camera reset */ + gpio_request(EVK_CAM_RESET, "cam-reset"); + gpio_direction_output(EVK_CAM_RESET, 1); + + /* TVIN reset */ + gpio_request(EVK_TVIN_RESET, "tvin-reset"); + gpio_direction_output(EVK_TVIN_RESET, 0); + msleep(5); + gpio_set_value(EVK_TVIN_RESET, 1); + + /* TVin power down */ + gpio_request(EVK_TVIN_PWR, "tvin-pwr"); + gpio_direction_output(EVK_TVIN_PWR, 0); + + /* CAN1 enable GPIO*/ + gpio_request(EVK_CAN1_EN1, "can1-en1"); + gpio_direction_output(EVK_CAN1_EN1, 0); + + gpio_request(EVK_CAN1_EN2, "can1-en2"); + gpio_direction_output(EVK_CAN1_EN2, 0); + + /* CAN2 enable GPIO*/ + gpio_request(EVK_CAN2_EN1, "can2-en1"); + gpio_direction_output(EVK_CAN2_EN1, 0); + + gpio_request(EVK_CAN2_EN2, "can2-en2"); + gpio_direction_output(EVK_CAN2_EN2, 0); + + if (enable_spdif) { + iomux_v3_cfg_t spdif_pin = MX53_PAD_GPIO_19__SPDIF_OUT1; + mxc_iomux_v3_setup_pad(spdif_pin); + } else { + /* GPIO for 12V */ + gpio_request(EVK_12V_EN, "12v-en"); + gpio_direction_output(EVK_12V_EN, 0); + } +} + static void __init mx53_evk_board_init(void) { - mxc_iomux_v3_setup_multiple_pads(mx53_evk_pads, - ARRAY_SIZE(mx53_evk_pads)); + mx53_evk_io_init(); + mx53_evk_init_uart(); mx53_evk_fec_reset(); imx53_add_fec(&mx53_evk_fec_pdata); + imx53_add_ipuv3(&ipu_data); + imx53_add_vpu(); + imx53_add_tve(&tve_data); + imx53_add_v4l2_output(0); + + if (!board_is_mx53_arm2()) { + imx53_add_mxc_pwm(1); + imx53_add_mxc_pwm_backlight(0, &evk_pwm_backlight_data); + } + + imx53_add_dvfs_core(&evk_dvfs_core_data); + imx53_add_busfreq(&evk_bus_freq_data); imx53_add_imx_i2c(0, &mx53_evk_i2c_data); imx53_add_imx_i2c(1, &mx53_evk_i2c_data); + i2c_register_board_info(0, mxc_i2c0_board_info, + ARRAY_SIZE(mxc_i2c0_board_info)); + i2c_register_board_info(1, mxc_i2c1_board_info, + ARRAY_SIZE(mxc_i2c1_board_info)); imx53_add_sdhci_esdhc_imx(0, NULL); imx53_add_sdhci_esdhc_imx(1, NULL); diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c old mode 100644 new mode 100755 index 1b947e8c9c0c..1ccc031b446a --- a/arch/arm/mach-mx5/board-mx53_loco.c +++ b/arch/arm/mach-mx5/board-mx53_loco.c @@ -20,12 +20,22 @@ #include #include +#include #include #include +#include +#include +#include +#include +#include #include #include +#include #include +#include +#include +#include #include #include @@ -33,11 +43,24 @@ #include "crm_regs.h" #include "devices-imx53.h" +#include "devices.h" +#include "usb.h" +#define LOCO_DISP0_PWR IMX_GPIO_NR(3, 24) +#define LOCO_DISP0_DET_INT IMX_GPIO_NR(3, 31) +#define LOCO_DISP0_RESET IMX_GPIO_NR(5, 0) #define MX53_LOCO_POWER IMX_GPIO_NR(1, 8) #define MX53_LOCO_UI1 IMX_GPIO_NR(2, 14) #define MX53_LOCO_UI2 IMX_GPIO_NR(2, 15) #define LOCO_FEC_PHY_RST IMX_GPIO_NR(7, 6) +#define LOCO_USBH1_VBUS IMX_GPIO_NR(7, 8) + +extern void __iomem *arm_plat_base; +extern void __iomem *gpc_base; +extern void __iomem *ccm_base; +extern void __iomem *imx_otg_base; + +extern int __init mx53_loco_init_da9052(void); static iomux_v3_cfg_t mx53_loco_pads[] = { /* FEC */ @@ -191,8 +214,8 @@ static iomux_v3_cfg_t mx53_loco_pads[] = { .wakeup = wake, \ } -static struct gpio_keys_button loco_buttons[] = { - GPIO_BUTTON(MX53_LOCO_POWER, KEY_POWER, 1, "power", 0), +static const struct gpio_keys_button loco_buttons[] __initconst = { + GPIO_BUTTON(MX53_LOCO_POWER, KEY_POWER, 1, "power", 1), GPIO_BUTTON(MX53_LOCO_UI1, KEY_VOLUMEUP, 1, "volume-up", 0), GPIO_BUTTON(MX53_LOCO_UI2, KEY_VOLUMEDOWN, 1, "volume-down", 0), }; @@ -225,18 +248,438 @@ static const struct imxi2c_platform_data mx53_loco_i2c_data __initconst = { .bitrate = 100000, }; -static void __init mx53_loco_board_init(void) +static struct i2c_board_info mxc_i2c0_board_info[] __initdata = { + { + .type = "mma8450", + .addr = 0x1C, + }, +}; + +static void sii902x_hdmi_reset(void) +{ + gpio_set_value(LOCO_DISP0_RESET, 0); + msleep(10); + gpio_set_value(LOCO_DISP0_RESET, 1); + msleep(10); +} + +static struct fsl_mxc_lcd_platform_data sii902x_hdmi_data = { + .reset = sii902x_hdmi_reset, +}; + +static void loco_suspend_enter(void) { + /* da9053 suspend preparation */ +} + +static void loco_suspend_exit(void) +{ + /*clear the EMPGC0/1 bits */ + __raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR); + __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR); + /* da9053 resmue resore */ +} + +static struct mxc_pm_platform_data loco_pm_data = { + .suspend_enter = loco_suspend_enter, + .suspend_exit = loco_suspend_exit, +}; + +static struct i2c_board_info mxc_i2c1_board_info[] __initdata = { + { + .type = "sgtl5000", + .addr = 0x0a, + }, + { + .type = "sii902x", + .addr = 0x39, + .irq = gpio_to_irq(LOCO_DISP0_DET_INT), + .platform_data = &sii902x_hdmi_data, + }, +}; + +static struct fb_videomode video_modes[] = { + { + /* 800x480 @ 57 Hz , pixel clk @ 27MHz */ + "CLAA-WVGA", 57, 800, 480, 37037, 40, 60, 10, 10, 20, 10, + FB_SYNC_CLK_LAT_FALL, + FB_VMODE_NONINTERLACED, + 0,}, + { + /* 800x480 @ 60 Hz , pixel clk @ 32MHz */ + "SEIKO-WVGA", 60, 800, 480, 29850, 89, 164, 23, 10, 10, 10, + FB_SYNC_CLK_LAT_FALL, + FB_VMODE_NONINTERLACED, + 0,}, + { + /* 1600x1200 @ 60 Hz 162M pixel clk*/ + "UXGA", 60, 1600, 1200, 6172, + 304, 64, + 1, 46, + 192, 3, + FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, + FB_VMODE_NONINTERLACED, + 0,}, +}; + +static struct ipuv3_fb_platform_data loco_fb_di0_data = { + .interface_pix_fmt = IPU_PIX_FMT_RGB565, + .mode_str = "CLAA-WVGA", + .modes = video_modes, + .num_modes = ARRAY_SIZE(video_modes), +}; + +static struct ipuv3_fb_platform_data loco_fb_di1_data = { + .interface_pix_fmt = IPU_PIX_FMT_GBR24, + .mode_str = "1024x768M-16@60", + .modes = video_modes, + .num_modes = ARRAY_SIZE(video_modes), +}; + +static struct imx_ipuv3_platform_data ipu_data = { + .rev = 3, + .fb_head0_platform_data = &loco_fb_di0_data, + .fb_head1_platform_data = &loco_fb_di1_data, +}; + +static struct platform_pwm_backlight_data loco_pwm_backlight_data = { + .pwm_id = 1, + .max_brightness = 255, + .dft_brightness = 128, + .pwm_period_ns = 50000, +}; + +static struct fsl_mxc_tve_platform_data tve_data = { + .dac_reg = "DA9052_LDO7", +}; + +static struct mxc_dvfs_platform_data loco_dvfs_core_data = { + .reg_id = "DA9052_BUCK_CORE", + .clk1_id = "cpu_clk", + .clk2_id = "gpc_dvfs_clk", + .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET, + .gpc_vcr_offset = MXC_GPC_VCR_OFFSET, + .ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET, + .ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET, + .ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET, + .prediv_mask = 0x1F800, + .prediv_offset = 11, + .prediv_val = 3, + .div3ck_mask = 0xE0000000, + .div3ck_offset = 29, + .div3ck_val = 2, + .emac_val = 0x08, + .upthr_val = 25, + .dnthr_val = 9, + .pncthr_val = 33, + .upcnt_val = 10, + .dncnt_val = 10, + .delay_time = 30, +}; + +static struct mxc_bus_freq_platform_data loco_bus_freq_data = { + .gp_reg_id = "DA9052_BUCK_CORE", + .lp_reg_id = "DA9052_BUCK_PRO", +}; + +static void mx53_loco_usbh1_vbus(bool on) +{ + if (on) + gpio_set_value(LOCO_USBH1_VBUS, 1); + else + gpio_set_value(LOCO_USBH1_VBUS, 0); +} + +static void __init mx53_loco_io_init(void) +{ + int ret; + + arm_plat_base = MX53_IO_ADDRESS(MX53_ARM_BASE_ADDR); + gpc_base = MX53_IO_ADDRESS(MX53_GPC_BASE_ADDR); + ccm_base = MX53_IO_ADDRESS(MX53_CCM_BASE_ADDR); + imx_otg_base = MX53_IO_ADDRESS(MX53_OTG_BASE_ADDR); + mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads, ARRAY_SIZE(mx53_loco_pads)); + + /* Sii902x HDMI controller */ + ret = gpio_request(LOCO_DISP0_RESET, "disp0-reset"); + if (ret) { + printk(KERN_ERR"failed to get GPIO_LOCO_DISP0_RESET: %d\n", ret); + return; + } + gpio_direction_output(LOCO_DISP0_RESET, 0); + + ret = gpio_request(LOCO_DISP0_DET_INT, "disp0-detect"); + if (ret) { + printk(KERN_ERR"failed to get GPIO_LOCO_DISP0_DET_INT: %d\n", ret); + return; + } + gpio_direction_input(LOCO_DISP0_DET_INT); + + /* enable disp0 power */ + ret = gpio_request(LOCO_DISP0_PWR, "disp0-power-en"); + if (ret) { + printk(KERN_ERR"failed to get GPIO_LOCO_DISP0_PWR: %d\n", ret); + return; + } + gpio_direction_output(LOCO_DISP0_PWR, 1); + + /* usb host1 vbus */ + ret = gpio_request(LOCO_USBH1_VBUS, "usbh1-vbus"); + if (ret) { + printk(KERN_ERR"failed to get GPIO LOCO_USBH1_VBUS: %d\n", ret); + return; + } + gpio_direction_output(LOCO_USBH1_VBUS, 0); +} + +/* HW Initialization, if return 0, initialization is successful. */ +static int sata_init(struct device *dev, void __iomem *addr) +{ + void __iomem *mmio; + struct clk *clk; + int ret = 0; + u32 tmpdata; + + clk = clk_get(dev, "imx_sata_clk"); + ret = IS_ERR(clk); + if (ret) { + printk(KERN_ERR "AHCI can't get clock.\n"); + return ret; + } + ret = clk_enable(clk); + if (ret) { + printk(KERN_ERR "AHCI can't enable clock.\n"); + clk_put(clk); + return ret; + } + + /* Get the AHB clock rate, and configure the TIMER1MS reg later */ + clk = clk_get(NULL, "ahb_clk"); + ret = IS_ERR(clk); + if (ret) { + printk(KERN_ERR "AHCI can't get AHB clock.\n"); + goto no_ahb_clk; + } + + mmio = ioremap(MX53_SATA_BASE_ADDR, SZ_2K); + if (mmio == NULL) { + printk(KERN_ERR "Failed to map SATA REGS\n"); + goto no_ahb_clk; + } + + tmpdata = readl(mmio + HOST_CAP); + if (!(tmpdata & HOST_CAP_SSS)) { + tmpdata |= HOST_CAP_SSS; + writel(tmpdata, mmio + HOST_CAP); + } + + if (!(readl(mmio + HOST_PORTS_IMPL) & 0x1)) + writel((readl(mmio + HOST_PORTS_IMPL) | 0x1), + mmio + HOST_PORTS_IMPL); + + tmpdata = clk_get_rate(clk) / 1000; + writel(tmpdata, mmio + HOST_TIMER1MS); + + clk = clk_get(dev, "usb_phy1_clk"); + ret = IS_ERR(clk); + if (ret) { + printk(KERN_ERR "AHCI can't get USB PHY1 CLK.\n"); + goto no_ahb_clk; + } + ret = clk_enable(clk); + if (ret) { + printk(KERN_ERR "AHCI Can't enable USB PHY1 clock.\n"); + clk_put(clk); + goto no_ahb_clk; + } + + /* Release resources when there is no device on the port */ + if ((readl(mmio + PORT_SATA_SR) & 0xF) == 0) { + iounmap(mmio); + ret = -ENODEV; + goto no_device; + } + + iounmap(mmio); + + return ret; + +no_device: + printk(KERN_INFO "NO SATA device is found, relase resource!\n"); + clk = clk_get(dev, "usb_phy1_clk"); + if (IS_ERR(clk)) { + clk = NULL; + printk(KERN_ERR "AHCI can't get USB PHY1 CLK.\n"); + } else { + clk_disable(clk); + clk_put(clk); + } + +no_ahb_clk: + clk = clk_get(dev, "imx_sata_clk"); + if (IS_ERR(clk)) { + clk = NULL; + printk(KERN_ERR "IMX SATA can't get clock.\n"); + } else { + clk_disable(clk); + clk_put(clk); + } + + return ret; +} + +static void sata_exit(struct device *dev) +{ + struct clk *clk; + + clk = clk_get(dev, "usb_phy1_clk"); + if (IS_ERR(clk)) { + clk = NULL; + printk(KERN_ERR "AHCI can't get USB PHY1 CLK.\n"); + } else { + clk_disable(clk); + clk_put(clk); + } + + clk = clk_get(dev, "imx_sata_clk"); + if (IS_ERR(clk)) { + clk = NULL; + printk(KERN_ERR "IMX SATA can't get clock.\n"); + } else { + clk_disable(clk); + clk_put(clk); + } +} + +static struct ahci_platform_data sata_data = { + .init = sata_init, + .exit = sata_exit, +}; + +static struct mxc_audio_platform_data loco_audio_data; + +static int loco_ssi_init(void) +{ + struct clk *ssi_ext1; + int rate; + + ssi_ext1 = clk_get(NULL, "ssi_ext1_clk"); + if (IS_ERR(ssi_ext1)) { + return -1; + } + rate = clk_round_rate(ssi_ext1, 24000000); + if (rate < 8000000 || rate > 27000000) { + printk(KERN_ERR "Error: SGTL5000 mclk freq %d out of range!\n", + rate); + clk_put(ssi_ext1); + return -1; + } + + loco_audio_data.sysclk = rate; + clk_set_rate(ssi_ext1, rate); + clk_enable(ssi_ext1); + + return 0; +} + +static struct imx_ssi_platform_data loco_ssi_pdata = { + .flags = IMX_SSI_DMA, +}; + +static struct mxc_audio_platform_data loco_audio_data = { + .ssi_num = 1, + .src_port = 2, + .ext_port = 5, + .init = loco_ssi_init, +}; + +static struct platform_device loco_audio_device = { + .name = "imx-sgtl5000", +}; + +static void mxc_iim_enable_fuse(void) +{ + u32 reg; + if (!ccm_base) + return; + /* enable fuse blown */ + reg = readl(ccm_base + 0x64); + reg |= 0x10; + writel(reg, ccm_base + 0x64); +} + +static void mxc_iim_disable_fuse(void) +{ + u32 reg; + if (!ccm_base) + return; + /* enable fuse blown */ + reg = readl(ccm_base + 0x64); + reg &= ~0x10; + writel(reg, ccm_base + 0x64); +} + +static struct mxc_iim_platform_data iim_data = { + .bank_start = MXC_IIM_MX53_BANK_START_ADDR, + .bank_end = MXC_IIM_MX53_BANK_END_ADDR, + .enable_fuse = mxc_iim_enable_fuse, + .disable_fuse = mxc_iim_disable_fuse, +}; + +static int z160_revision __initdata; + +static void __init mx53_loco_board_init(void) +{ + mx53_loco_io_init(); + imx53_add_imx_uart(0, NULL); mx53_loco_fec_reset(); imx53_add_fec(&mx53_loco_fec_data); + + mxc_register_device(&mxc_pm_device, &loco_pm_data); + + imx53_add_ipuv3(&ipu_data); + imx53_add_vpu(); + imx53_add_tve(&tve_data); + imx53_add_v4l2_output(0); + + imx53_add_mxc_pwm(1); + imx53_add_mxc_pwm_backlight(0, &loco_pwm_backlight_data); + imx53_add_imx2_wdt(0, NULL); + imx53_add_srtc(); + imx53_add_dvfs_core(&loco_dvfs_core_data); + imx53_add_busfreq(&loco_bus_freq_data); imx53_add_imx_i2c(0, &mx53_loco_i2c_data); imx53_add_imx_i2c(1, &mx53_loco_i2c_data); + + mx53_loco_init_da9052(); + i2c_register_board_info(0, mxc_i2c0_board_info, + ARRAY_SIZE(mxc_i2c0_board_info)); + i2c_register_board_info(1, mxc_i2c1_board_info, + ARRAY_SIZE(mxc_i2c1_board_info)); + imx53_add_sdhci_esdhc_imx(0, NULL); imx53_add_sdhci_esdhc_imx(2, NULL); + imx53_add_ahci_imx(0, &sata_data); + imx53_add_iim(&iim_data); + + /* USB */ + mx5_usb_dr_init(); + mx5_set_host1_vbus_func(mx53_loco_usbh1_vbus); + mx5_usbh1_init(); + + mxc_register_device(&loco_audio_device, &loco_audio_data); + imx53_add_imx_ssi(1, &loco_ssi_pdata); + + /*GPU*/ + if (mx53_revision() >= IMX_CHIP_REVISION_2_0) + z160_revision = 1; + else + z160_revision = 0; + imx53_add_mxc_gpu(&z160_revision); imx_add_gpio_keys(&loco_button_data); } diff --git a/arch/arm/mach-mx5/board-mx53_smd.c b/arch/arm/mach-mx5/board-mx53_smd.c old mode 100644 new mode 100755 index 817c08938f55..e5e3f002ad38 --- a/arch/arm/mach-mx5/board-mx53_smd.c +++ b/arch/arm/mach-mx5/board-mx53_smd.c @@ -20,12 +20,19 @@ #include #include +#include #include #include +#include +#include +#include +#include #include #include +#include #include +#include #include #include @@ -33,8 +40,24 @@ #include "crm_regs.h" #include "devices-imx53.h" +#include "devices.h" +#include "usb.h" + #define SMD_FEC_PHY_RST IMX_GPIO_NR(7, 6) +#define MX53_SMD_SD1_WP IMX_GPIO_NR(4, 11) +#define MX53_SMD_HDMI_RESET_B IMX_GPIO_NR(5, 0) +#define MX53_SMD_MODEM_RESET_B IMX_GPIO_NR(5, 2) +#define MX53_SMD_KEY_INT IMX_GPIO_NR(5, 4) +#define MX53_SMD_HDMI_INT IMX_GPIO_NR(6, 12) +#define MX53_SMD_CAP_TCH_INT1 IMX_GPIO_NR(3, 20) +#define MX53_SMD_SATA_PWR_EN IMX_GPIO_NR(3, 3) +#define MX53_SMD_OTG_VBUS IMX_GPIO_NR(7, 8) +#define MX53_SMD_NONKEY IMX_GPIO_NR(1, 8) +#define MX53_SMD_UI1 IMX_GPIO_NR(2, 14) +#define MX53_SMD_UI2 IMX_GPIO_NR(2, 15) + +extern int mx53_smd_init_da9052(void); static iomux_v3_cfg_t mx53_smd_pads[] = { MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, @@ -50,13 +73,22 @@ static iomux_v3_cfg_t mx53_smd_pads[] = { /* I2C1 */ MX53_PAD_CSI0_DAT8__I2C1_SDA, MX53_PAD_CSI0_DAT9__I2C1_SCL, - /* SD1 */ + /* I2C2 */ + MX53_PAD_KEY_COL3__I2C2_SCL, + MX53_PAD_KEY_ROW3__I2C2_SDA, + /* I2C3 */ + MX53_PAD_GPIO_3__I2C3_SCL, + MX53_PAD_GPIO_6__I2C3_SDA, + + /* SD1_CD */ + MX53_PAD_EIM_DA13__GPIO3_13, MX53_PAD_SD1_CMD__ESDHC1_CMD, MX53_PAD_SD1_CLK__ESDHC1_CLK, MX53_PAD_SD1_DATA0__ESDHC1_DAT0, MX53_PAD_SD1_DATA1__ESDHC1_DAT1, MX53_PAD_SD1_DATA2__ESDHC1_DAT2, MX53_PAD_SD1_DATA3__ESDHC1_DAT3, + /* SD2 */ MX53_PAD_SD2_CMD__ESDHC2_CMD, MX53_PAD_SD2_CLK__ESDHC2_CLK, @@ -64,6 +96,7 @@ static iomux_v3_cfg_t mx53_smd_pads[] = { MX53_PAD_SD2_DATA1__ESDHC2_DAT1, MX53_PAD_SD2_DATA2__ESDHC2_DAT2, MX53_PAD_SD2_DATA3__ESDHC2_DAT3, + /* SD3 */ MX53_PAD_PATA_DATA8__ESDHC3_DAT0, MX53_PAD_PATA_DATA9__ESDHC3_DAT1, @@ -75,8 +108,57 @@ static iomux_v3_cfg_t mx53_smd_pads[] = { MX53_PAD_PATA_DATA3__ESDHC3_DAT7, MX53_PAD_PATA_IORDY__ESDHC3_CLK, MX53_PAD_PATA_RESET_B__ESDHC3_CMD, + + /* SATA_PWR_EN */ + MX53_PAD_EIM_DA3__GPIO3_3, + + /* USB_OTG_OC */ + MX53_PAD_EIM_DA12__GPIO3_12, + /* USB_HUB_RESET_B */ + MX53_PAD_EIM_DA14__GPIO3_14, + /* USB_OTG_PWR_EN */ + MX53_PAD_PATA_DA_2__GPIO7_8, +}; + +#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) +#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake) \ +{ \ + .gpio = gpio_num, \ + .type = EV_KEY, \ + .code = ev_code, \ + .active_low = act_low, \ + .desc = "btn " descr, \ + .wakeup = wake, \ +} + +static struct gpio_keys_button smd_buttons[] = { + GPIO_BUTTON(MX53_SMD_NONKEY, KEY_POWER, 1, "power", 0), + GPIO_BUTTON(MX53_SMD_UI1, KEY_VOLUMEUP, 1, "volume-up", 0), + GPIO_BUTTON(MX53_SMD_UI2, KEY_VOLUMEDOWN, 1, "volume-down", 0), +}; + +static struct gpio_keys_platform_data smd_button_data = { + .buttons = smd_buttons, + .nbuttons = ARRAY_SIZE(smd_buttons), +}; + +static struct platform_device smd_button_device = { + .name = "gpio-keys", + .id = -1, + .num_resources = 0, + .dev = { + .platform_data = &smd_button_data, + } }; +static void __init smd_add_device_buttons(void) +{ + platform_device_register(&smd_button_device); +} +#else +static void __init smd_add_device_buttons(void) {} +#endif + static const struct imxuart_platform_data mx53_smd_uart_data __initconst = { .flags = IMXUART_HAVE_RTSCTS, }; @@ -111,18 +193,319 @@ static const struct imxi2c_platform_data mx53_smd_i2c_data __initconst = { .bitrate = 100000, }; +static void smd_suspend_enter(void) +{ + /* da9053 suspend preparation */ +} + +static void smd_suspend_exit(void) +{ + /*clear the EMPGC0/1 bits */ + __raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR); + __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR); + /* da9053 resmue resore */ +} + +static struct mxc_pm_platform_data smd_pm_data = { + .suspend_enter = smd_suspend_enter, + .suspend_exit = smd_suspend_exit, +}; + + +static const struct esdhc_platform_data mx53_smd_sd1_data __initconst = { + .wp_gpio = MX53_SMD_SD1_WP, +}; + +static struct fsl_mxc_camera_platform_data camera_data = { + .analog_regulator = "DA9052_LDO7", + .core_regulator = "DA9052_LDO9", + .mclk = 24000000, + .csi = 0, +}; + +static struct i2c_board_info mxc_i2c0_board_info[] __initdata = { + { + .type = "mma8451", + .addr = 0x1C, + }, + { + .type = "ov3640", + .addr = 0x3C, + .platform_data = (void *)&camera_data, + }, +}; + +static u16 smd_touchkey_martix[4] = { + KEY_BACK, KEY_HOME, KEY_MENU, KEY_SEARCH, +}; + +static struct mpr121_platform_data mpr121_keyboard_platdata = { + .keycount = ARRAY_SIZE(smd_touchkey_martix), + .vdd_uv = 3300000, + .matrix = smd_touchkey_martix, +}; + +static struct i2c_board_info mxc_i2c1_board_info[] __initdata = { + { + .type = "sgtl5000", + .addr = 0x0a, + }, + { + .type = "mpr121_touchkey", + .addr = 0x5a, + .irq = gpio_to_irq(MX53_SMD_KEY_INT), + .platform_data = &mpr121_keyboard_platdata, + }, +}; + +static void mxc_iim_enable_fuse(void) +{ + u32 reg; + if (!ccm_base) + return; + /* enable fuse blown */ + reg = readl(ccm_base + 0x64); + reg |= 0x10; + writel(reg, ccm_base + 0x64); +} + +static void mxc_iim_disable_fuse(void) +{ + u32 reg; + if (!ccm_base) + return; + /* enable fuse blown */ + reg = readl(ccm_base + 0x64); + reg &= ~0x10; + writel(reg, ccm_base + 0x64); +} + + +static struct mxc_iim_platform_data iim_data = { + .bank_start = MXC_IIM_MX53_BANK_START_ADDR, + .bank_end = MXC_IIM_MX53_BANK_END_ADDR, + .enable_fuse = mxc_iim_enable_fuse, + .disable_fuse = mxc_iim_disable_fuse, +}; + + +static void sii9022_hdmi_reset(void) +{ + gpio_set_value(MX53_SMD_HDMI_RESET_B, 0); + msleep(10); + gpio_set_value(MX53_SMD_HDMI_RESET_B, 1); + msleep(10); +} + +static struct fsl_mxc_lcd_platform_data sii902x_hdmi_data = { + .reset = sii9022_hdmi_reset, +}; + +static struct i2c_board_info mxc_i2c2_board_info[] __initdata = { + { + .type = "sii902x", + .addr = 0x39, + .irq = gpio_to_irq(MX53_SMD_HDMI_INT), + .platform_data = &sii902x_hdmi_data, + }, + { + I2C_BOARD_INFO("p1003_ts", 0x41), + .irq = gpio_to_irq(MX53_SMD_CAP_TCH_INT1), + }, +}; + +/* HW Initialization, if return 0, initialization is successful. */ +static int sata_init(struct device *dev, void __iomem *addr) +{ + void __iomem *mmio; + struct clk *clk; + int ret = 0; + u32 tmpdata; + + /* Enable SATA PWR */ + ret = gpio_request(MX53_SMD_SATA_PWR_EN, "ahci-sata-pwr"); + if (ret) { + printk(KERN_ERR "failed to get SATA_PWR_EN: %d\n", ret); + return ret; + } + gpio_direction_output(MX53_SMD_SATA_PWR_EN, 1); + + clk = clk_get(dev, "imx_sata_clk"); + ret = IS_ERR(clk); + if (ret) { + printk(KERN_ERR "AHCI can't get clock.\n"); + return ret; + } + ret = clk_enable(clk); + if (ret) { + printk(KERN_ERR "AHCI can't enable clock.\n"); + clk_put(clk); + return ret; + } + + /* Get the AHB clock rate, and configure the TIMER1MS reg later */ + clk = clk_get(NULL, "ahb_clk"); + ret = IS_ERR(clk); + if (ret) { + printk(KERN_ERR "AHCI can't get AHB clock.\n"); + goto no_ahb_clk; + } + + mmio = ioremap(MX53_SATA_BASE_ADDR, SZ_2K); + if (mmio == NULL) { + printk(KERN_ERR "Failed to map SATA REGS\n"); + goto no_ahb_clk; + } + + tmpdata = readl(mmio + HOST_CAP); + if (!(tmpdata & HOST_CAP_SSS)) { + tmpdata |= HOST_CAP_SSS; + writel(tmpdata, mmio + HOST_CAP); + } + + if (!(readl(mmio + HOST_PORTS_IMPL) & 0x1)) + writel((readl(mmio + HOST_PORTS_IMPL) | 0x1), + mmio + HOST_PORTS_IMPL); + + tmpdata = clk_get_rate(clk) / 1000; + writel(tmpdata, mmio + HOST_TIMER1MS); + + clk = clk_get(dev, "usb_phy1_clk"); + ret = IS_ERR(clk); + if (ret) { + printk(KERN_ERR "AHCI can't get USB PHY1 CLK.\n"); + goto no_ahb_clk; + } + ret = clk_enable(clk); + if (ret) { + printk(KERN_ERR "AHCI Can't enable USB PHY1 clock.\n"); + clk_put(clk); + goto no_ahb_clk; + } + + /* Release resources when there is no device on the port */ + if ((readl(mmio + PORT_SATA_SR) & 0xF) == 0) { + iounmap(mmio); + ret = -ENODEV; + goto no_device; + } + + iounmap(mmio); + + return ret; + +no_device: + printk(KERN_INFO "NO SATA device is found, relase resource!\n"); + clk = clk_get(dev, "usb_phy1_clk"); + if (IS_ERR(clk)) { + clk = NULL; + printk(KERN_ERR "AHCI can't get USB PHY1 CLK.\n"); + } else { + clk_disable(clk); + clk_put(clk); + } + +no_ahb_clk: + clk = clk_get(dev, "imx_sata_clk"); + if (IS_ERR(clk)) { + clk = NULL; + printk(KERN_ERR "IMX SATA can't get clock.\n"); + } else { + clk_disable(clk); + clk_put(clk); + } + + return ret; +} + +static void sata_exit(struct device *dev) +{ + struct clk *clk; + + clk = clk_get(dev, "usb_phy1_clk"); + if (IS_ERR(clk)) { + clk = NULL; + printk(KERN_ERR "AHCI can't get USB PHY1 CLK.\n"); + } else { + clk_disable(clk); + clk_put(clk); + } + + clk = clk_get(dev, "imx_sata_clk"); + if (IS_ERR(clk)) { + clk = NULL; + printk(KERN_ERR "IMX SATA can't get clock.\n"); + } else { + clk_disable(clk); + clk_put(clk); + } +} + +static struct ahci_platform_data sata_data = { + .init = sata_init, + .exit = sata_exit, +}; + +static void mx53_smd_usbotg_vbus(bool on) +{ + if (on) + gpio_set_value(MX53_SMD_OTG_VBUS, 1); + else + gpio_set_value(MX53_SMD_OTG_VBUS, 0); +} + +static void __init mx53_smd_init_usb(void) +{ + int ret = 0; + + imx_otg_base = MX53_IO_ADDRESS(MX53_OTG_BASE_ADDR); + ret = gpio_request(MX53_SMD_OTG_VBUS, "usb-pwr"); + if (ret) { + printk(KERN_ERR"failed to get GPIO SMD_OTG_VBUS: %d\n", ret); + return; + } + gpio_direction_output(MX53_SMD_OTG_VBUS, 0); + + mx5_set_otghost_vbus_func(mx53_smd_usbotg_vbus); + mx5_usb_dr_init(); + mx5_usbh1_init(); +} + +static struct imx_ssi_platform_data smd_ssi_pdata = { + .flags = IMX_SSI_DMA, +}; + static void __init mx53_smd_board_init(void) { mxc_iomux_v3_setup_multiple_pads(mx53_smd_pads, ARRAY_SIZE(mx53_smd_pads)); mx53_smd_init_uart(); mx53_smd_fec_reset(); + mxc_register_device(&mxc_pm_device, &smd_pm_data); imx53_add_fec(&mx53_smd_fec_data); imx53_add_imx2_wdt(0, NULL); + imx53_add_srtc(); imx53_add_imx_i2c(0, &mx53_smd_i2c_data); + imx53_add_imx_i2c(1, &mx53_smd_i2c_data); + imx53_add_imx_i2c(2, &mx53_smd_i2c_data); imx53_add_sdhci_esdhc_imx(0, NULL); - imx53_add_sdhci_esdhc_imx(1, NULL); + imx53_add_sdhci_esdhc_imx(1, &mx53_smd_sd1_data); imx53_add_sdhci_esdhc_imx(2, NULL); + imx53_add_ahci_imx(0, &sata_data); + + mx53_smd_init_usb(); + imx53_add_iim(&iim_data); + smd_add_device_buttons(); + + mx53_smd_init_da9052(); + i2c_register_board_info(0, mxc_i2c0_board_info, + ARRAY_SIZE(mxc_i2c0_board_info)); + i2c_register_board_info(1, mxc_i2c1_board_info, + ARRAY_SIZE(mxc_i2c1_board_info)); + i2c_register_board_info(2, mxc_i2c2_board_info, + ARRAY_SIZE(mxc_i2c2_board_info)); + + imx53_add_imx_ssi(0, &smd_ssi_pdata); } static void __init mx53_smd_timer_init(void) -- 2.39.5