From 764f2c73aaf363dc04743da980807b3f8572fba1 Mon Sep 17 00:00:00 2001 From: Sandor Yu Date: Mon, 2 Dec 2013 15:40:46 +0800 Subject: [PATCH] ENGR00290337 ipuv3: Setup pixel clock tree after ipu reset When the ipu pixel clocks are initialized, the default pixel clock rate will be calucated according to the present ipu register setting which is likely set by a bootloader. But these registers will be reset by the ipu reset function. If the default pixel clock rate is the same to what is requested later, the clk_set_rate function will treat this case as pixel clock unchanged. Move the pixel clock setup function after the ipu reset function to resolve this issue Signed-off-by: Sandor Yu --- drivers/mxc/ipu3/ipu_common.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/mxc/ipu3/ipu_common.c b/drivers/mxc/ipu3/ipu_common.c index e8b4fba9ce41..b1930398ece5 100644 --- a/drivers/mxc/ipu3/ipu_common.c +++ b/drivers/mxc/ipu3/ipu_common.c @@ -464,12 +464,6 @@ static int ipu_probe(struct platform_device *pdev) } ipu->online = true; - ret = ipu_clk_setup_enable(ipu, pltfm_data); - if (ret < 0) { - dev_err(ipu->dev, "ipu clk setup failed\n"); - ipu->online = false; - return ret; - } platform_set_drvdata(pdev, ipu); @@ -489,6 +483,14 @@ static int ipu_probe(struct platform_device *pdev) IPU_DISP_GEN); } + /* setup ipu clk tree after ipu reset */ + ret = ipu_clk_setup_enable(ipu, pltfm_data); + if (ret < 0) { + dev_err(ipu->dev, "ipu clk setup failed\n"); + ipu->online = false; + return ret; + } + /* Set sync refresh channels and CSI->mem channel as high priority */ ipu_idmac_write(ipu, 0x18800001L, IDMAC_CHA_PRI(0)); -- 2.39.5