From 7e3eb599236db605413b4e047692dab9b600d6c6 Mon Sep 17 00:00:00 2001 From: "Nagaraju, Vathsala" Date: Fri, 9 Dec 2016 23:42:09 +0530 Subject: [PATCH] drm/i915/psr: report psr2 hw enabled from psr2_ctl For PSR2 , as per spec, PSR2_CTL bit 31 to be set. for psr1, bit 31 in SRD_CTL to be set. Reporting "HW Enabled & Active bit" status for psr2 from SRD_CTL gives wrong status. Cc: Rodrigo Vivi Cc: Jim Bride Signed-off-by: vathsala nagaraju Reviewed-by: Rodrigo Vivi Signed-off-by: Rodrigo Vivi Link: http://patchwork.freedesktop.org/patch/msgid/1481307129-29354-1-git-send-email-vathsala.nagaraju@intel.com --- drivers/gpu/drm/i915/i915_debugfs.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index a746130c8e32..54e196d9d83e 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2567,9 +2567,12 @@ static int i915_edp_psr_status(struct seq_file *m, void *data) seq_printf(m, "Re-enable work scheduled: %s\n", yesno(work_busy(&dev_priv->psr.work.work))); - if (HAS_DDI(dev_priv)) - enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE; - else { + if (HAS_DDI(dev_priv)) { + if (dev_priv->psr.psr2_support) + enabled = I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE; + else + enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE; + } else { for_each_pipe(dev_priv, pipe) { enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, pipe); -- 2.39.5