From 7f4174f27cb15ff6810c44be7d6a327842631d24 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Fri, 14 Oct 2011 09:40:52 +0800 Subject: [PATCH] ARM: at91: pit add DT support Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- .../devicetree/bindings/arm/at91.txt | 7 ++++ arch/arm/boot/dts/at91sam9g20.dtsi | 6 +++ arch/arm/boot/dts/at91sam9g45.dtsi | 6 +++ arch/arm/mach-at91/at91sam926x_time.c | 42 ++++++++++++++++++- 4 files changed, 59 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/at91.txt diff --git a/Documentation/devicetree/bindings/arm/at91.txt b/Documentation/devicetree/bindings/arm/at91.txt new file mode 100644 index 000000000000..cdefffd4b3a5 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/at91.txt @@ -0,0 +1,7 @@ +Atmel AT91 device tree bindings. +======================================== + +PIT Timers required properties: + - compatible = "atmel,at91sam9260-pit" + - interrupts : The single IRQ line for the timer. + - reg : The register bank for the timer. diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi index aeef04269cf8..410ae6e8f535 100644 --- a/arch/arm/boot/dts/at91sam9g20.dtsi +++ b/arch/arm/boot/dts/at91sam9g20.dtsi @@ -54,6 +54,12 @@ reg = <0xfffff000 0x200>; }; + pit: timer@fffffd30 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xfffffd30 0xf>; + interrupts = <1>; + }; + dbgu: serial@fffff200 { compatible = "atmel,at91sam9260-usart"; reg = <0xfffff200 0x200>; diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index db6a45202f26..a09b102cc3ae 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -53,6 +53,12 @@ reg = <0xfffff000 0x200>; }; + pit: timer@fffffd30 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xfffffd30 0xf>; + interrupts = <1>; + }; + dma: dma-controller@ffffec00 { compatible = "atmel,at91sam9g45-dma"; reg = <0xffffec00 0x200>; diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c index d89ead740a99..d4b80ec0184d 100644 --- a/arch/arm/mach-at91/at91sam926x_time.c +++ b/arch/arm/mach-at91/at91sam926x_time.c @@ -14,6 +14,8 @@ #include #include #include +#include +#include #include @@ -133,7 +135,8 @@ static irqreturn_t at91sam926x_pit_interrupt(int irq, void *dev_id) static struct irqaction at91sam926x_pit_irq = { .name = "at91_tick", .flags = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, - .handler = at91sam926x_pit_interrupt + .handler = at91sam926x_pit_interrupt, + .irq = AT91_ID_SYS, }; static void at91sam926x_pit_reset(void) @@ -149,6 +152,39 @@ static void at91sam926x_pit_reset(void) pit_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN); } +#ifdef CONFIG_OF +static struct of_device_id timer_ids[] = { + { .compatible = "atmel,at91sam9260-pit" }, +}; + +int __init of_at91sam926x_pit_init(void) +{ + struct device_node *np; + const unsigned int *intspec; + + np = of_find_matching_node(NULL, timer_ids); + if (!np) + return -EINVAL; + pit_base_addr = of_iomap(np, 0); + if (!pit_base_addr) + return -EINVAL; + + /* Get the interrupts property */ + intspec = of_get_property(np, "interrupts", NULL); + BUG_ON(!intspec); + at91sam926x_pit_irq.irq = be32_to_cpup(intspec); + + of_node_put(np); + + return 0; +} +#else +static int __init of_at91sam926x_pit_init(void) +{ + return -EINVAL; +} +#endif + /* * Set up both clocksource and clockevent support. */ @@ -177,7 +213,7 @@ static void __init at91sam926x_pit_init(void) clocksource_register_hz(&pit_clk, pit_rate); /* Set up irq handler */ - setup_irq(AT91_ID_SYS, &at91sam926x_pit_irq); + setup_irq(at91sam926x_pit_irq.irq, &at91sam926x_pit_irq); /* Set up and register clockevents */ pit_clkevt.mult = div_sc(pit_rate, NSEC_PER_SEC, pit_clkevt.shift); @@ -193,6 +229,8 @@ static void at91sam926x_pit_suspend(void) void __init at91sam926x_ioremap_pit(u32 addr) { + if (!of_at91sam926x_pit_init()) + return; pit_base_addr = ioremap(addr, 16); if (!pit_base_addr) -- 2.39.5