From 8574de861978d5187da4f2b7dcf127a5795e967f Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 20 Jan 2015 14:44:58 +0100 Subject: [PATCH] ARM: dts: r8a7791: Add SYSC PM Domains Add a device node for the System Controller. Hook up the Cortex-A15 CPU cores and the Cortex-A15 L2 cache/SCU to their respective PM Domains. Signed-off-by: Geert Uytterhoeven Acked-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 6d4a0b6e4df9..e30200c9476a 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -13,6 +13,7 @@ #include #include #include +#include / { compatible = "renesas,r8a7791"; @@ -51,6 +52,7 @@ voltage-tolerance = <1>; /* 1% */ clocks = <&cpg_clocks R8A7791_CLK_Z>; clock-latency = <300000>; /* 300 us */ + power-domains = <&sysc R8A7791_PD_CA15_CPU0>; next-level-cache = <&L2_CA15>; /* kHz - uV - OPPs unknown yet */ @@ -67,6 +69,7 @@ compatible = "arm,cortex-a15"; reg = <1>; clock-frequency = <1500000000>; + power-domains = <&sysc R8A7791_PD_CA15_CPU1>; next-level-cache = <&L2_CA15>; }; }; @@ -92,6 +95,7 @@ L2_CA15: cache-controller@0 { compatible = "cache"; + power-domains = <&sysc R8A7791_PD_CA15_SCU>; cache-unified; cache-level = <2>; }; @@ -1466,6 +1470,12 @@ }; }; + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7791-sysc"; + reg = <0 0xe6180000 0 0x0200>; + #power-domain-cells = <1>; + }; + qspi: spi@e6b10000 { compatible = "renesas,qspi-r8a7791", "renesas,qspi"; reg = <0 0xe6b10000 0 0x2c>; -- 2.39.5