From 857b8bd8cdd22407f9378761be41ad93225c2747 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Tue, 10 Sep 2013 16:22:20 -0400 Subject: [PATCH] ENGR00278941-1: arm: imx: Fix suspend/resume unstable issue As we need to float DDR IO when entering DSM, so those registers we need to access after DDR IO is floated must be contained in TLB, otherwise, the TLB update may case DDR access and lead to system hang. To make sure these registers' address is in TLB, we need to flush TLB first then access them manually. Signed-off-by: Anson Huang --- arch/arm/mach-imx/pm-imx6.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c index dc638a533948..1efe20c5f27d 100644 --- a/arch/arm/mach-imx/pm-imx6.c +++ b/arch/arm/mach-imx/pm-imx6.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include @@ -212,6 +213,7 @@ static int imx6_suspend_finish(unsigned long val) * call low level suspend function in iram, * as we need to float DDR IO. */ + local_flush_tlb_all(); suspend_in_iram_fn(suspend_iram_base, iram_paddr, cpu_type); return 0; } -- 2.39.5