From 85922e54a3a14a6aee6c0b1fc67d81ef0c60fc9c Mon Sep 17 00:00:00 2001 From: Oskar Schirmer Date: Thu, 17 Feb 2011 16:42:58 +0100 Subject: [PATCH] arm: tcc8k: Choose PLL settings conforming to board layout The evaluation board is driven with 1.2V core voltage, so system clock must not exceed 192 MHz, bus clock must not exceed 110 MHz. Choose appropriate values and set DTCMWAIT accordingly. Adapt UART setting to avoid console log interruption and wait for the specified locking time of 300us to pass. Signed-off-by: Oskar Schirmer Cc: bigeasy@linutronix.de Signed-off-by: Thomas Gleixner --- arch/arm/mach-tcc8k/board-tcc8000-sdk.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/mach-tcc8k/board-tcc8000-sdk.c b/arch/arm/mach-tcc8k/board-tcc8000-sdk.c index a3b66d405eb3..c25cf3f84566 100644 --- a/arch/arm/mach-tcc8k/board-tcc8000-sdk.c +++ b/arch/arm/mach-tcc8k/board-tcc8000-sdk.c @@ -6,6 +6,7 @@ * published by the Free Software Foundation. */ +#include #include #include #include @@ -18,6 +19,7 @@ #include #include +#include #include "common.h" @@ -52,6 +54,22 @@ static struct sys_timer tcc8k_timer = { static void __init tcc8k_map_io(void) { tcc8k_map_common_io(); + + /* set PLL0 clock to 96MHz, adapt UART0 divisor */ + __raw_writel(0x00026003, CKC_BASE + PLL0CFG_OFFS); + __raw_writel(0x10000001, CKC_BASE + ACLKUART0_OFFS); + + /* set PLL1 clock to 192MHz */ + __raw_writel(0x00016003, CKC_BASE + PLL1CFG_OFFS); + + /* set PLL2 clock to 48MHz */ + __raw_writel(0x00036003, CKC_BASE + PLL2CFG_OFFS); + + /* with CPU freq higher than 150 MHz, need extra DTCM wait */ + __raw_writel(0x00000001, SCFG_BASE + DTCMWAIT_OFFS); + + /* PLL locking time as specified */ + udelay(300); } MACHINE_START(TCC8000_SDK, "Telechips TCC8000-SDK Demo Board") -- 2.39.5