From 8d41794c6fc61ac2f09b5c25267e2c68748326cc Mon Sep 17 00:00:00 2001 From: Peter Daifuku Date: Tue, 26 Aug 2014 17:11:36 +0200 Subject: [PATCH] PCI: tegra: Fix extended configuration space mapping The 16 chunks of 64 KiB that need to be stitched together to make up the configuration space for one bus (1 MiB) are located 24 bits (== 16 MiB) apart in physical address space. This is determined by the start of the extended register field (bits 24-27) in the physical mapping. Tested-by: Stephen Warren Signed-off-by: Peter Daifuku Signed-off-by: Thierry Reding Signed-off-by: Bjorn Helgaas --- drivers/pci/host/pci-tegra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c index 42241b5bdf02..6329be3d4695 100644 --- a/drivers/pci/host/pci-tegra.c +++ b/drivers/pci/host/pci-tegra.c @@ -383,7 +383,7 @@ static struct tegra_pcie_bus *tegra_pcie_bus_alloc(struct tegra_pcie *pcie, for (i = 0; i < 16; i++) { unsigned long virt = (unsigned long)bus->area->addr + i * SZ_64K; - phys_addr_t phys = cs + i * SZ_1M + busnr * SZ_64K; + phys_addr_t phys = cs + i * SZ_16M + busnr * SZ_64K; err = ioremap_page_range(virt, virt + SZ_64K, phys, prot); if (err < 0) { -- 2.39.5