From 8e685072e9995242acb31bbf5d6b73b9000cfdc1 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Wed, 3 Aug 2011 09:47:32 +0800 Subject: [PATCH] ENGR00154211 [MX6]Add workaround for wdog errata Errata number:TKT039676 WDOG sw reset is generated by writing to its control register. WDOG's reset is activated by ipg_clk_s, and is de-activated (later) by a synchronized CKIL (32KHz clock). On the other hand SRC samples the WDOG reset with an unsynchronized CKIL clock. If the write to WDOG control register happens between the edges of unsynchronized and synchronized CKIL clocks SRC will miss the wdog reset pulse. Workaround: write wdog control register twice. Signed-off-by: Anson Huang --- arch/arm/plat-mxc/system.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c index 383013c7c76d..cadf3bb23275 100644 --- a/arch/arm/plat-mxc/system.c +++ b/arch/arm/plat-mxc/system.c @@ -43,6 +43,10 @@ void arch_reset(char mode, const char *cmd) /* wait for reset to assert... */ wcr_enable = (1 << 2); __raw_writew(wcr_enable, wdog_base); + /* errata TKT039676, SRS bit may be missed when + SRC sample it, need to write the wdog controller + twice to avoid it */ + __raw_writew(wcr_enable, wdog_base); /* wait for reset to assert... */ mdelay(500); -- 2.39.5