From 8e6ac20338228dc77c8f3538efb5a3aba712e0e5 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Mon, 14 Apr 2014 15:47:03 +0200 Subject: [PATCH] ARM: mvebu: enable the ARM SCU on Armada 375 and Armada 38x Contrary to the Armada 370 and XP that used the PJ4B Marvell cores, the Armada 375 and Armada 38x use the ARM Cortex-A9. A consequence of this is that the unit responsible for the coherency between CPUs is now the ARM SCU, and not the Marvell coherency unit (which is still present to do coherency with I/O devices). Therefore this commit: * Ensures that the selection of the Armada 375 or Armada 38x SoC support enables the ARM SCU support in the kernel. * Make sure to initialize the SCU at boot time. Signed-off-by: Thomas Petazzoni Link: https://lkml.kernel.org/r/1397483228-25625-6-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper --- arch/arm/mach-mvebu/Kconfig | 2 ++ arch/arm/mach-mvebu/board-v7.c | 19 +++++++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 475cf8a6d165..736bd2cbc1f0 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -40,6 +40,7 @@ config MACH_ARMADA_375 select ARM_GIC select ARMADA_375_CLK select CPU_V7 + select HAVE_ARM_SCU select MACH_MVEBU_V7 select PINCTRL_ARMADA_375 help @@ -53,6 +54,7 @@ config MACH_ARMADA_38X select ARM_GIC select ARMADA_38X_CLK select CPU_V7 + select HAVE_ARM_SCU select MACH_MVEBU_V7 select PINCTRL_ARMADA_38X help diff --git a/arch/arm/mach-mvebu/board-v7.c b/arch/arm/mach-mvebu/board-v7.c index 1730e0cdb6f6..85f964e55bf3 100644 --- a/arch/arm/mach-mvebu/board-v7.c +++ b/arch/arm/mach-mvebu/board-v7.c @@ -27,11 +27,29 @@ #include #include #include +#include #include "armada-370-xp.h" #include "common.h" #include "coherency.h" #include "mvebu-soc-id.h" +/* + * Enables the SCU when available. Obviously, this is only useful on + * Cortex-A based SOCs, not on PJ4B based ones. + */ +static void __init mvebu_scu_enable(void) +{ + void __iomem *scu_base; + + struct device_node *np = + of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu"); + if (np) { + scu_base = of_iomap(np, 0); + scu_enable(scu_base); + of_node_put(np); + } +} + /* * Early versions of Armada 375 SoC have a bug where the BootROM * leaves an external data abort pending. The kernel is hit by this @@ -57,6 +75,7 @@ static void __init mvebu_timer_and_clk_init(void) { of_clk_init(NULL); clocksource_of_init(); + mvebu_scu_enable(); coherency_init(); BUG_ON(mvebu_mbus_dt_init(coherency_available())); #ifdef CONFIG_CACHE_L2X0 -- 2.39.5