From 9f50ac9a1682c1f24d002acb2d1cdfa5403fdc3a Mon Sep 17 00:00:00 2001 From: Peter Turczak Date: Tue, 9 Aug 2011 14:11:19 +1000 Subject: [PATCH] m68knommu: fix problems with SPI/GPIO on ColdFire 520x The problem has its root in the calculation of the set-port offsets (macro MCFGPIO_SETR() in arch/m68k/include/asm/gpio.h), this assumes that all ports have the same offset from the base port address (MCFGPIO_SETR) which is defined in mcf520xsim.h as an alias of MCFGIO_PSETR_BUSCTL. Because the BUSCTL and BE port do not have a set-register (see MCF5208 Reference Manual Page 13-10, Table 13-3) the offset calculations went wrong. Because the BE and BUSCTL port do not seem useful in these parts, as they lack a set register, I removed them and adapted the gpio chip bases which are also used for the offset-calculations. Now both setting and resetting the chip selects works as expected from userland and from the kernelspace. Signed-off-by: Peter Turczak Signed-off-by: Greg Ungerer --- arch/m68k/include/asm/m520xsim.h | 26 ++++++++--------- arch/m68k/include/asm/mcfqspi.h | 8 +++-- arch/m68k/platform/520x/config.c | 6 ++-- arch/m68k/platform/520x/gpio.c | 50 +++++--------------------------- 4 files changed, 27 insertions(+), 63 deletions(-) diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h index b6bf2c518bac..eda62de7e607 100644 --- a/arch/m68k/include/asm/m520xsim.h +++ b/arch/m68k/include/asm/m520xsim.h @@ -90,15 +90,13 @@ #define MCFGPIO_PDDR_FECH 0xFC0A4013 #define MCFGPIO_PDDR_FECL 0xFC0A4014 -#define MCFGPIO_PPDSDR_BUSCTL 0xFC0A401A -#define MCFGPIO_PPDSDR_BE 0xFC0A401B -#define MCFGPIO_PPDSDR_CS 0xFC0A401C -#define MCFGPIO_PPDSDR_FECI2C 0xFC0A401D -#define MCFGPIO_PPDSDR_QSPI 0xFC0A401E -#define MCFGPIO_PPDSDR_TIMER 0xFC0A401F -#define MCFGPIO_PPDSDR_UART 0xFC0A4021 -#define MCFGPIO_PPDSDR_FECH 0xFC0A4021 -#define MCFGPIO_PPDSDR_FECL 0xFC0A4022 +#define MCFGPIO_PPDSDR_CS 0xFC0A401A +#define MCFGPIO_PPDSDR_FECI2C 0xFC0A401B +#define MCFGPIO_PPDSDR_QSPI 0xFC0A401C +#define MCFGPIO_PPDSDR_TIMER 0xFC0A401D +#define MCFGPIO_PPDSDR_UART 0xFC0A401E +#define MCFGPIO_PPDSDR_FECH 0xFC0A401F +#define MCFGPIO_PPDSDR_FECL 0xFC0A4020 #define MCFGPIO_PCLRR_BUSCTL 0xFC0A4024 #define MCFGPIO_PCLRR_BE 0xFC0A4025 @@ -113,11 +111,11 @@ /* * Generic GPIO support */ -#define MCFGPIO_PODR MCFGPIO_PODR_BUSCTL -#define MCFGPIO_PDDR MCFGPIO_PDDR_BUSCTL -#define MCFGPIO_PPDR MCFGPIO_PPDSDR_BUSCTL -#define MCFGPIO_SETR MCFGPIO_PPDSDR_BUSCTL -#define MCFGPIO_CLRR MCFGPIO_PCLRR_BUSCTL +#define MCFGPIO_PODR MCFGPIO_PODR_CS +#define MCFGPIO_PDDR MCFGPIO_PDDR_CS +#define MCFGPIO_PPDR MCFGPIO_PPDSDR_CS +#define MCFGPIO_SETR MCFGPIO_PPDSDR_CS +#define MCFGPIO_CLRR MCFGPIO_PCLRR_CS #define MCFGPIO_PIN_MAX 80 #define MCFGPIO_IRQ_MAX 8 diff --git a/arch/m68k/include/asm/mcfqspi.h b/arch/m68k/include/asm/mcfqspi.h index 39d90d51111d..7fe631972f1f 100644 --- a/arch/m68k/include/asm/mcfqspi.h +++ b/arch/m68k/include/asm/mcfqspi.h @@ -24,9 +24,11 @@ #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) #define MCFQSPI_IOBASE (MCF_IPSBAR + 0x340) #elif defined(CONFIG_M5249) -#define MCFQSPI_IOBASE (MCF_MBAR + 0x300) -#elif defined(CONFIG_M520x) || defined(CONFIG_M532x) -#define MCFQSPI_IOBASE 0xFC058000 +#define MCFQSPI_IOBASE (MCF_MBAR + 0x300) +#elif defined(CONFIG_M520x) +#define MCFQSPI_IOBASE 0xFC05C000 +#elif defined(CONFIG_M532x) +#define MCFQSPI_IOBASE 0xFC058000 #endif #define MCFQSPI_IOSIZE 0x40 diff --git a/arch/m68k/platform/520x/config.c b/arch/m68k/platform/520x/config.c index 621238f1a219..8a98683f1b15 100644 --- a/arch/m68k/platform/520x/config.c +++ b/arch/m68k/platform/520x/config.c @@ -91,9 +91,9 @@ static struct resource m520x_qspi_resources[] = { }, }; -#define MCFQSPI_CS0 62 -#define MCFQSPI_CS1 63 -#define MCFQSPI_CS2 44 +#define MCFQSPI_CS0 46 +#define MCFQSPI_CS1 47 +#define MCFQSPI_CS2 27 static int m520x_cs_setup(struct mcfqspi_cs_control *cs_control) { diff --git a/arch/m68k/platform/520x/gpio.c b/arch/m68k/platform/520x/gpio.c index d757328563d1..9bcc3e4b60c5 100644 --- a/arch/m68k/platform/520x/gpio.c +++ b/arch/m68k/platform/520x/gpio.c @@ -36,42 +36,6 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .podr = (void __iomem *) MCFEPORT_EPDR, .ppdr = (void __iomem *) MCFEPORT_EPPDR, }, - { - .gpio_chip = { - .label = "BUSCTL", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 8, - .ngpio = 4, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_BUSCTL, - .podr = (void __iomem *) MCFGPIO_PODR_BUSCTL, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL, - .setr = (void __iomem *) MCFGPIO_PPDSDR_BUSCTL, - .clrr = (void __iomem *) MCFGPIO_PCLRR_BUSCTL, - }, - { - .gpio_chip = { - .label = "BE", - .request = mcf_gpio_request, - .free = mcf_gpio_free, - .direction_input = mcf_gpio_direction_input, - .direction_output = mcf_gpio_direction_output, - .get = mcf_gpio_get_value, - .set = mcf_gpio_set_value_fast, - .base = 16, - .ngpio = 4, - }, - .pddr = (void __iomem *) MCFGPIO_PDDR_BE, - .podr = (void __iomem *) MCFGPIO_PODR_BE, - .ppdr = (void __iomem *) MCFGPIO_PPDSDR_BE, - .setr = (void __iomem *) MCFGPIO_PPDSDR_BE, - .clrr = (void __iomem *) MCFGPIO_PCLRR_BE, - }, { .gpio_chip = { .label = "CS", @@ -81,7 +45,7 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .direction_output = mcf_gpio_direction_output, .get = mcf_gpio_get_value, .set = mcf_gpio_set_value_fast, - .base = 25, + .base = 9, .ngpio = 3, }, .pddr = (void __iomem *) MCFGPIO_PDDR_CS, @@ -99,7 +63,7 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .direction_output = mcf_gpio_direction_output, .get = mcf_gpio_get_value, .set = mcf_gpio_set_value_fast, - .base = 32, + .base = 16, .ngpio = 4, }, .pddr = (void __iomem *) MCFGPIO_PDDR_FECI2C, @@ -117,7 +81,7 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .direction_output = mcf_gpio_direction_output, .get = mcf_gpio_get_value, .set = mcf_gpio_set_value_fast, - .base = 40, + .base = 24, .ngpio = 4, }, .pddr = (void __iomem *) MCFGPIO_PDDR_QSPI, @@ -135,7 +99,7 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .direction_output = mcf_gpio_direction_output, .get = mcf_gpio_get_value, .set = mcf_gpio_set_value_fast, - .base = 48, + .base = 32, .ngpio = 4, }, .pddr = (void __iomem *) MCFGPIO_PDDR_TIMER, @@ -153,7 +117,7 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .direction_output = mcf_gpio_direction_output, .get = mcf_gpio_get_value, .set = mcf_gpio_set_value_fast, - .base = 56, + .base = 40, .ngpio = 8, }, .pddr = (void __iomem *) MCFGPIO_PDDR_UART, @@ -171,7 +135,7 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .direction_output = mcf_gpio_direction_output, .get = mcf_gpio_get_value, .set = mcf_gpio_set_value_fast, - .base = 64, + .base = 48, .ngpio = 8, }, .pddr = (void __iomem *) MCFGPIO_PDDR_FECH, @@ -189,7 +153,7 @@ static struct mcf_gpio_chip mcf_gpio_chips[] = { .direction_output = mcf_gpio_direction_output, .get = mcf_gpio_get_value, .set = mcf_gpio_set_value_fast, - .base = 72, + .base = 56, .ngpio = 8, }, .pddr = (void __iomem *) MCFGPIO_PDDR_FECL, -- 2.39.5