From a190bb70f871bdc5a720c94c2b5b63382dcd722e Mon Sep 17 00:00:00 2001 From: Mahesh Mahadevan Date: Thu, 27 Oct 2011 06:52:46 -0500 Subject: [PATCH] ENGR00160930-4 Add support for MX6 Sabre-lite Updated the IOMUX Pad settings. Updated the UART settings for Sabre-lite. Added Board define incase we need to identify different board revisions Signed-off-by: Mahesh Mahadevan --- arch/arm/plat-mxc/include/mach/iomux-mx6q.h | 10 ++++++---- arch/arm/plat-mxc/include/mach/mxc.h | 7 +++++++ arch/arm/plat-mxc/include/mach/uncompress.h | 4 ++++ 3 files changed, 17 insertions(+), 4 deletions(-) diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx6q.h b/arch/arm/plat-mxc/include/mach/iomux-mx6q.h index 778354e1e621..f6281bbae106 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx6q.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx6q.h @@ -3977,7 +3977,7 @@ typedef enum iomux_config { #define MX6Q_PAD_EIM_D21__GPIO_3_21 \ (_MX6Q_PAD_EIM_D21__GPIO_3_21 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_EIM_D21__I2C1_SCL \ - (_MX6Q_PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(NO_PAD_CTRL)) + (_MX6Q_PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) #define MX6Q_PAD_EIM_D21__SPDIF_IN1 \ (_MX6Q_PAD_EIM_D21__SPDIF_IN1 | MUX_PAD_CTRL(NO_PAD_CTRL)) @@ -4113,7 +4113,7 @@ typedef enum iomux_config { #define MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 \ (_MX6Q_PAD_EIM_D28__WEIM_WEIM_D_28 | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_EIM_D28__I2C1_SDA \ - (_MX6Q_PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(NO_PAD_CTRL)) + (_MX6Q_PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(MX6Q_I2C_PAD_CTRL)) #define MX6Q_PAD_EIM_D28__ECSPI4_MOSI \ (_MX6Q_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_EIM_D28__IPU2_CSI1_D_12 \ @@ -5182,7 +5182,8 @@ typedef enum iomux_config { #define MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED \ (_MX6Q_PAD_ENET_MDIO__RESERVED_RESERVED | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_ENET_MDIO__ENET_MDIO \ - (_MX6Q_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(NO_PAD_CTRL)) + (_MX6Q_PAD_ENET_MDIO__ENET_MDIO | \ + MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) #define MX6Q_PAD_ENET_MDIO__ESAI1_SCKR \ (_MX6Q_PAD_ENET_MDIO__ESAI1_SCKR | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL)) #define MX6Q_PAD_ENET_MDIO__SDMA_DEBUG_BUS_DEVICE_3 \ @@ -5313,7 +5314,8 @@ typedef enum iomux_config { #define MX6Q_PAD_ENET_MDC__MLB_MLBDAT \ (_MX6Q_PAD_ENET_MDC__MLB_MLBDAT | MUX_PAD_CTRL(NO_PAD_CTRL)) #define MX6Q_PAD_ENET_MDC__ENET_MDC \ - (_MX6Q_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(NO_PAD_CTRL)) + (_MX6Q_PAD_ENET_MDC__ENET_MDC | \ + MUX_PAD_CTRL(MX6Q_ENET_PAD_CTRL)) #define MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 \ (_MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0 | MUX_PAD_CTRL(MX6Q_ESAI_PAD_CTRL)) #define MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN \ diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h index fb698ca63a0f..4a3bf3bd8d6f 100755 --- a/arch/arm/plat-mxc/include/mach/mxc.h +++ b/arch/arm/plat-mxc/include/mach/mxc.h @@ -83,6 +83,13 @@ extern unsigned int system_rev; #define board_is_mx53_evk_b() (cpu_is_mx53() && board_is_rev(IMX_BOARD_REV_3)) #endif +#ifdef CONFIG_SOC_IMX6Q +#define board_is_mx6q_arm2() (cpu_is_mx6q() && \ + board_is_rev(IMX_BOARD_REV_1)) +#define board_is_mx6q_sabre_lite() (cpu_is_mx6q() && \ + board_is_rev(IMX_BOARD_REV_2)) +#endif + #ifndef __ASSEMBLY__ extern unsigned int __mxc_cpu_type; #endif diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h index 756ab7581bdb..8f0bfaa46a49 100644 --- a/arch/arm/plat-mxc/include/mach/uncompress.h +++ b/arch/arm/plat-mxc/include/mach/uncompress.h @@ -67,6 +67,7 @@ static inline void flush(void) #define MX50_UART1_BASE_ADDR 0x53fbc000 #define MX53_UART1_BASE_ADDR 0x53fbc000 #define MX6Q_UART4_BASE_ADDR 0x021f0000 +#define MX6Q_UART2_BASE_ADDR 0x021e8000 static __inline__ void __arch_decomp_setup(unsigned long arch_id) { @@ -123,6 +124,9 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id) case MACH_TYPE_MX6Q_ARM2: uart_base = MX6Q_UART4_BASE_ADDR; break; + case MACH_TYPE_MX6Q_SABRELITE: + uart_base = MX6Q_UART2_BASE_ADDR; + break; default: break; } -- 2.39.5