From a816d250e866b01bd18b0dd2bcbe5f1951310094 Mon Sep 17 00:00:00 2001 From: Ulf Hansson Date: Wed, 10 Oct 2012 13:42:27 +0200 Subject: [PATCH] clk: ux500: Support for prcmu_scalable_rate clock The prcmu_scalable_rate clock can change rate but is not gateable. Signed-off-by: Ulf Hansson Acked-by: Linus Walleij Signed-off-by: Mike Turquette --- drivers/clk/ux500/clk-prcmu.c | 17 +++++++++++++++++ drivers/clk/ux500/clk.h | 6 ++++++ 2 files changed, 23 insertions(+) diff --git a/drivers/clk/ux500/clk-prcmu.c b/drivers/clk/ux500/clk-prcmu.c index 04577ca6a308..74faa7e3cf59 100644 --- a/drivers/clk/ux500/clk-prcmu.c +++ b/drivers/clk/ux500/clk-prcmu.c @@ -187,6 +187,13 @@ static struct clk_ops clk_prcmu_gate_ops = { .recalc_rate = clk_prcmu_recalc_rate, }; +static struct clk_ops clk_prcmu_scalable_rate_ops = { + .is_enabled = clk_prcmu_is_enabled, + .recalc_rate = clk_prcmu_recalc_rate, + .round_rate = clk_prcmu_round_rate, + .set_rate = clk_prcmu_set_rate, +}; + static struct clk_ops clk_prcmu_rate_ops = { .is_enabled = clk_prcmu_is_enabled, .recalc_rate = clk_prcmu_recalc_rate, @@ -278,6 +285,16 @@ struct clk *clk_reg_prcmu_gate(const char *name, &clk_prcmu_gate_ops); } +struct clk *clk_reg_prcmu_scalable_rate(const char *name, + const char *parent_name, + u8 cg_sel, + unsigned long rate, + unsigned long flags) +{ + return clk_reg_prcmu(name, parent_name, cg_sel, rate, flags, + &clk_prcmu_scalable_rate_ops); +} + struct clk *clk_reg_prcmu_rate(const char *name, const char *parent_name, u8 cg_sel, diff --git a/drivers/clk/ux500/clk.h b/drivers/clk/ux500/clk.h index f36eeedca493..c3e449169a83 100644 --- a/drivers/clk/ux500/clk.h +++ b/drivers/clk/ux500/clk.h @@ -35,6 +35,12 @@ struct clk *clk_reg_prcmu_gate(const char *name, u8 cg_sel, unsigned long flags); +struct clk *clk_reg_prcmu_scalable_rate(const char *name, + const char *parent_name, + u8 cg_sel, + unsigned long rate, + unsigned long flags); + struct clk *clk_reg_prcmu_rate(const char *name, const char *parent_name, u8 cg_sel, -- 2.39.5