From a92ee7763ed4bd4bb7d884f5aad6c9b320087205 Mon Sep 17 00:00:00 2001 From: Steve Cornelius Date: Fri, 19 Oct 2012 13:18:37 -0700 Subject: [PATCH] ENGR00230538-1: CAAM: Correct shifting offset for CAAM IPG clock selection 3 pairs of clock enable bits are required for CAAM clocking: (1) wrapper IPG clock (2) wrapper ACLK (3) secure memory clock IPG enable happened to be using an incorrect shift selection, which had the net effect of leaving secure memory unclocked. Added the correct shift selection in so that all 3 clock enable pairs are turned on. Signed-off-by: Steve Cornelius Signed-off-by: Terry Lv --- arch/arm/mach-mx6/clock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c index 67c3d1fa6fd1..bbddb94cd774 100644 --- a/arch/arm/mach-mx6/clock.c +++ b/arch/arm/mach-mx6/clock.c @@ -4244,7 +4244,7 @@ static struct clk caam_clk[] = { __INIT_CLK_DEBUG(caam_ipg_clk) .id = 2, .enable_reg = MXC_CCM_CCGR0, - .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET, + .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET, .enable = _clk_enable, .disable = _clk_disable, .parent = &mmdc_ch0_axi_clk[0], -- 2.39.5