From abbdf7aaef4c536c4764c9e29088c9d84ac4aec7 Mon Sep 17 00:00:00 2001 From: Danny Nold Date: Thu, 17 May 2012 15:17:37 -0500 Subject: [PATCH] ENGR00209883-1 - EPDC fb: Add support for MX 6SoloLite ARM2 board - Add EPDC and Max17135 structures and initialization calls to the MX6SL ARM2 board file - Add IOMUX configuration defines and GPIO defines for EPDC/Max17135 - Remove prints/debug from EPDC-related clocks. Signed-off-by: Danny Nold --- arch/arm/mach-mx6/board-mx6sl_arm2.c | 460 ++++++++++++++++++++++++++- arch/arm/mach-mx6/board-mx6sl_arm2.h | 80 +++++ arch/arm/mach-mx6/clock_mx6sl.c | 3 - 3 files changed, 539 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-mx6/board-mx6sl_arm2.c b/arch/arm/mach-mx6/board-mx6sl_arm2.c index eb4245a51a98..628fb7d4d778 100755 --- a/arch/arm/mach-mx6/board-mx6sl_arm2.c +++ b/arch/arm/mach-mx6/board-mx6sl_arm2.c @@ -83,6 +83,47 @@ #define MX6_ARM2_SD3_CD IMX_GPIO_NR(3, 22) /* REF_CLK_32K */ #define MX6_ARM2_FEC_PWR_EN IMX_GPIO_NR(4, 21) /* FEC_TX_CLK */ +/* EPDC GPIO pins */ +#define MX6SL_ARM2_EPDC_SDDO_0 IMX_GPIO_NR(1, 7) +#define MX6SL_ARM2_EPDC_SDDO_1 IMX_GPIO_NR(1, 8) +#define MX6SL_ARM2_EPDC_SDDO_2 IMX_GPIO_NR(1, 9) +#define MX6SL_ARM2_EPDC_SDDO_3 IMX_GPIO_NR(1, 10) +#define MX6SL_ARM2_EPDC_SDDO_4 IMX_GPIO_NR(1, 11) +#define MX6SL_ARM2_EPDC_SDDO_5 IMX_GPIO_NR(1, 12) +#define MX6SL_ARM2_EPDC_SDDO_6 IMX_GPIO_NR(1, 13) +#define MX6SL_ARM2_EPDC_SDDO_7 IMX_GPIO_NR(1, 14) +#define MX6SL_ARM2_EPDC_SDDO_8 IMX_GPIO_NR(1, 15) +#define MX6SL_ARM2_EPDC_SDDO_9 IMX_GPIO_NR(1, 16) +#define MX6SL_ARM2_EPDC_SDDO_10 IMX_GPIO_NR(1, 17) +#define MX6SL_ARM2_EPDC_SDDO_11 IMX_GPIO_NR(1, 18) +#define MX6SL_ARM2_EPDC_SDDO_12 IMX_GPIO_NR(1, 19) +#define MX6SL_ARM2_EPDC_SDDO_13 IMX_GPIO_NR(1, 20) +#define MX6SL_ARM2_EPDC_SDDO_14 IMX_GPIO_NR(1, 21) +#define MX6SL_ARM2_EPDC_SDDO_15 IMX_GPIO_NR(1, 22) +#define MX6SL_ARM2_EPDC_GDCLK IMX_GPIO_NR(1, 31) +#define MX6SL_ARM2_EPDC_GDSP IMX_GPIO_NR(2, 2) +#define MX6SL_ARM2_EPDC_GDOE IMX_GPIO_NR(2, 0) +#define MX6SL_ARM2_EPDC_GDRL IMX_GPIO_NR(2, 1) +#define MX6SL_ARM2_EPDC_SDCLK IMX_GPIO_NR(1, 23) +#define MX6SL_ARM2_EPDC_SDOE IMX_GPIO_NR(1, 25) +#define MX6SL_ARM2_EPDC_SDLE IMX_GPIO_NR(1, 24) +#define MX6SL_ARM2_EPDC_SDSHR IMX_GPIO_NR(1, 26) +#define MX6SL_ARM2_EPDC_PWRCOM IMX_GPIO_NR(2, 11) +#define MX6SL_ARM2_EPDC_PWRSTAT IMX_GPIO_NR(2, 13) +#define MX6SL_ARM2_EPDC_PWRCTRL0 IMX_GPIO_NR(2, 7) +#define MX6SL_ARM2_EPDC_PWRCTRL1 IMX_GPIO_NR(2, 8) +#define MX6SL_ARM2_EPDC_PWRCTRL2 IMX_GPIO_NR(2, 9) +#define MX6SL_ARM2_EPDC_PWRCTRL3 IMX_GPIO_NR(2, 10) +#define MX6SL_ARM2_EPDC_BDR0 IMX_GPIO_NR(2, 5) +#define MX6SL_ARM2_EPDC_BDR1 IMX_GPIO_NR(2, 6) +#define MX6SL_ARM2_EPDC_SDCE0 IMX_GPIO_NR(1, 27) +#define MX6SL_ARM2_EPDC_SDCE1 IMX_GPIO_NR(1, 28) +#define MX6SL_ARM2_EPDC_SDCE2 IMX_GPIO_NR(1, 29) +#define MX6SL_ARM2_EPDC_PMIC_WAKE IMX_GPIO_NR(2, 14) /* EPDC_PWRWAKEUP */ +#define MX6SL_ARM2_EPDC_PMIC_INT IMX_GPIO_NR(2, 12) /* EPDC_PWRINT */ +#define MX6SL_ARM2_EPDC_VCOM IMX_GPIO_NR(2, 3) + +static int max17135_regulator_init(struct max17135 *max17135); extern int __init mx6sl_arm2_init_pfuze100(u32 int_gpio); static const struct esdhc_platform_data mx6_arm2_sd1_data __initconst = { .cd_gpio = MX6_ARM2_SD1_CD, @@ -105,6 +146,175 @@ static const struct esdhc_platform_data mx6_arm2_sd3_data __initconst = { .delay_line = 0, }; +#define mV_to_uV(mV) (mV * 1000) +#define uV_to_mV(uV) (uV / 1000) +#define V_to_uV(V) (mV_to_uV(V * 1000)) +#define uV_to_V(uV) (uV_to_mV(uV) / 1000) + +static struct regulator_consumer_supply display_consumers[] = { + { + /* MAX17135 */ + .supply = "DISPLAY", + }, +}; + +static struct regulator_consumer_supply vcom_consumers[] = { + { + /* MAX17135 */ + .supply = "VCOM", + }, +}; + +static struct regulator_consumer_supply v3p3_consumers[] = { + { + /* MAX17135 */ + .supply = "V3P3", + }, +}; + +static struct regulator_init_data max17135_init_data[] = { + { + .constraints = { + .name = "DISPLAY", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(display_consumers), + .consumer_supplies = display_consumers, + }, { + .constraints = { + .name = "GVDD", + .min_uV = V_to_uV(20), + .max_uV = V_to_uV(20), + }, + }, { + .constraints = { + .name = "GVEE", + .min_uV = V_to_uV(-22), + .max_uV = V_to_uV(-22), + }, + }, { + .constraints = { + .name = "HVINN", + .min_uV = V_to_uV(-22), + .max_uV = V_to_uV(-22), + }, + }, { + .constraints = { + .name = "HVINP", + .min_uV = V_to_uV(20), + .max_uV = V_to_uV(20), + }, + }, { + .constraints = { + .name = "VCOM", + .min_uV = mV_to_uV(-4325), + .max_uV = mV_to_uV(-500), + .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | + REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(vcom_consumers), + .consumer_supplies = vcom_consumers, + }, { + .constraints = { + .name = "VNEG", + .min_uV = V_to_uV(-15), + .max_uV = V_to_uV(-15), + }, + }, { + .constraints = { + .name = "VPOS", + .min_uV = V_to_uV(15), + .max_uV = V_to_uV(15), + }, + }, { + .constraints = { + .name = "V3P3", + .valid_ops_mask = REGULATOR_CHANGE_STATUS, + }, + .num_consumer_supplies = ARRAY_SIZE(v3p3_consumers), + .consumer_supplies = v3p3_consumers, + }, +}; + +static struct platform_device max17135_sensor_device = { + .name = "max17135_sensor", + .id = 0, +}; + +static struct max17135_platform_data max17135_pdata __initdata = { + .vneg_pwrup = 1, + .gvee_pwrup = 1, + .vpos_pwrup = 2, + .gvdd_pwrup = 1, + .gvdd_pwrdn = 1, + .vpos_pwrdn = 2, + .gvee_pwrdn = 1, + .vneg_pwrdn = 1, + .gpio_pmic_pwrgood = MX6SL_ARM2_EPDC_PWRSTAT, + .gpio_pmic_vcom_ctrl = MX6SL_ARM2_EPDC_VCOM, + .gpio_pmic_wakeup = MX6SL_ARM2_EPDC_PMIC_WAKE, + .gpio_pmic_v3p3 = MX6SL_ARM2_EPDC_PWRCTRL0, + .gpio_pmic_intr = MX6SL_ARM2_EPDC_PMIC_INT, + .regulator_init = max17135_init_data, + .init = max17135_regulator_init, +}; + +static int __init max17135_regulator_init(struct max17135 *max17135) +{ + struct max17135_platform_data *pdata = &max17135_pdata; + int i, ret; + + max17135->gvee_pwrup = pdata->gvee_pwrup; + max17135->vneg_pwrup = pdata->vneg_pwrup; + max17135->vpos_pwrup = pdata->vpos_pwrup; + max17135->gvdd_pwrup = pdata->gvdd_pwrup; + max17135->gvdd_pwrdn = pdata->gvdd_pwrdn; + max17135->vpos_pwrdn = pdata->vpos_pwrdn; + max17135->vneg_pwrdn = pdata->vneg_pwrdn; + max17135->gvee_pwrdn = pdata->gvee_pwrdn; + + max17135->max_wait = pdata->vpos_pwrup + pdata->vneg_pwrup + + pdata->gvdd_pwrup + pdata->gvee_pwrup; + + max17135->gpio_pmic_pwrgood = pdata->gpio_pmic_pwrgood; + max17135->gpio_pmic_vcom_ctrl = pdata->gpio_pmic_vcom_ctrl; + max17135->gpio_pmic_wakeup = pdata->gpio_pmic_wakeup; + max17135->gpio_pmic_v3p3 = pdata->gpio_pmic_v3p3; + max17135->gpio_pmic_intr = pdata->gpio_pmic_intr; + + gpio_request(max17135->gpio_pmic_wakeup, "epdc-pmic-wake"); + gpio_direction_output(max17135->gpio_pmic_wakeup, 0); + + gpio_request(max17135->gpio_pmic_vcom_ctrl, "epdc-vcom"); + gpio_direction_output(max17135->gpio_pmic_vcom_ctrl, 0); + + gpio_request(max17135->gpio_pmic_v3p3, "epdc-v3p3"); + gpio_direction_output(max17135->gpio_pmic_v3p3, 0); + + gpio_request(max17135->gpio_pmic_intr, "epdc-pmic-int"); + gpio_direction_input(max17135->gpio_pmic_intr); + + gpio_request(max17135->gpio_pmic_pwrgood, "epdc-pwrstat"); + gpio_direction_input(max17135->gpio_pmic_pwrgood); + + max17135->vcom_setup = false; + max17135->init_done = false; + + for (i = 0; i < MAX17135_NUM_REGULATORS; i++) { + ret = max17135_register_regulator(max17135, i, + &pdata->regulator_init[i]); + if (ret != 0) { + printk(KERN_ERR"max17135 regulator init failed: %d\n", + ret); + return ret; + } + } + + regulator_has_full_constraints(); + + return 0; +} + static struct imxi2c_platform_data mx6_arm2_i2c0_data = { .bitrate = 100000, }; @@ -120,7 +330,7 @@ static struct imxi2c_platform_data mx6_arm2_i2c2_data = { static struct i2c_board_info mxc_i2c0_board_info[] __initdata = { { I2C_BOARD_INFO("max17135", 0x48), - /*.platform_data = &max17135_pdata,*/ + .platform_data = &max17135_pdata, }, }; @@ -135,6 +345,7 @@ static struct i2c_board_info mxc_i2c2_board_info[] __initdata = { { }, }; + void __init early_console_setup(unsigned long base, struct clk *clk); static inline void mx6_arm2_init_uart(void) @@ -150,6 +361,248 @@ static struct fec_platform_data fec_data __initdata = { .phy = PHY_INTERFACE_MODE_RMII, }; +static int epdc_get_pins(void) +{ + int ret = 0; + + /* Claim GPIOs for EPDC pins - used during power up/down */ + ret |= gpio_request(MX6SL_ARM2_EPDC_SDDO_0, "epdc_d0"); + ret |= gpio_request(MX6SL_ARM2_EPDC_SDDO_1, "epdc_d1"); + ret |= gpio_request(MX6SL_ARM2_EPDC_SDDO_2, "epdc_d2"); + ret |= gpio_request(MX6SL_ARM2_EPDC_SDDO_3, "epdc_d3"); + ret |= gpio_request(MX6SL_ARM2_EPDC_SDDO_4, "epdc_d4"); + ret |= gpio_request(MX6SL_ARM2_EPDC_SDDO_5, "epdc_d5"); + ret |= gpio_request(MX6SL_ARM2_EPDC_SDDO_6, "epdc_d6"); + ret |= gpio_request(MX6SL_ARM2_EPDC_SDDO_7, "epdc_d7"); + ret |= gpio_request(MX6SL_ARM2_EPDC_GDCLK, "epdc_gdclk"); + ret |= gpio_request(MX6SL_ARM2_EPDC_GDSP, "epdc_gdsp"); + ret |= gpio_request(MX6SL_ARM2_EPDC_GDOE, "epdc_gdoe"); + ret |= gpio_request(MX6SL_ARM2_EPDC_GDRL, "epdc_gdrl"); + ret |= gpio_request(MX6SL_ARM2_EPDC_SDCLK, "epdc_sdclk"); + ret |= gpio_request(MX6SL_ARM2_EPDC_SDOE, "epdc_sdoe"); + ret |= gpio_request(MX6SL_ARM2_EPDC_SDLE, "epdc_sdle"); + ret |= gpio_request(MX6SL_ARM2_EPDC_SDSHR, "epdc_sdshr"); + ret |= gpio_request(MX6SL_ARM2_EPDC_BDR0, "epdc_bdr0"); + ret |= gpio_request(MX6SL_ARM2_EPDC_SDCE0, "epdc_sdce0"); + ret |= gpio_request(MX6SL_ARM2_EPDC_SDCE1, "epdc_sdce1"); + ret |= gpio_request(MX6SL_ARM2_EPDC_SDCE2, "epdc_sdce2"); + + return ret; +} + +static void epdc_put_pins(void) +{ + gpio_free(MX6SL_ARM2_EPDC_SDDO_0); + gpio_free(MX6SL_ARM2_EPDC_SDDO_1); + gpio_free(MX6SL_ARM2_EPDC_SDDO_2); + gpio_free(MX6SL_ARM2_EPDC_SDDO_3); + gpio_free(MX6SL_ARM2_EPDC_SDDO_4); + gpio_free(MX6SL_ARM2_EPDC_SDDO_5); + gpio_free(MX6SL_ARM2_EPDC_SDDO_6); + gpio_free(MX6SL_ARM2_EPDC_SDDO_7); + gpio_free(MX6SL_ARM2_EPDC_GDCLK); + gpio_free(MX6SL_ARM2_EPDC_GDSP); + gpio_free(MX6SL_ARM2_EPDC_GDOE); + gpio_free(MX6SL_ARM2_EPDC_GDRL); + gpio_free(MX6SL_ARM2_EPDC_SDCLK); + gpio_free(MX6SL_ARM2_EPDC_SDOE); + gpio_free(MX6SL_ARM2_EPDC_SDLE); + gpio_free(MX6SL_ARM2_EPDC_SDSHR); + gpio_free(MX6SL_ARM2_EPDC_BDR0); + gpio_free(MX6SL_ARM2_EPDC_SDCE0); + gpio_free(MX6SL_ARM2_EPDC_SDCE1); + gpio_free(MX6SL_ARM2_EPDC_SDCE2); +} + +static void epdc_enable_pins(void) +{ + /* Configure MUX settings to enable EPDC use */ + mxc_iomux_v3_setup_multiple_pads(mx6sl_arm2_epdc_enable_pads, \ + ARRAY_SIZE(mx6sl_arm2_epdc_enable_pads)); + + gpio_direction_input(MX6SL_ARM2_EPDC_SDDO_0); + gpio_direction_input(MX6SL_ARM2_EPDC_SDDO_1); + gpio_direction_input(MX6SL_ARM2_EPDC_SDDO_2); + gpio_direction_input(MX6SL_ARM2_EPDC_SDDO_3); + gpio_direction_input(MX6SL_ARM2_EPDC_SDDO_4); + gpio_direction_input(MX6SL_ARM2_EPDC_SDDO_5); + gpio_direction_input(MX6SL_ARM2_EPDC_SDDO_6); + gpio_direction_input(MX6SL_ARM2_EPDC_SDDO_7); + gpio_direction_input(MX6SL_ARM2_EPDC_GDCLK); + gpio_direction_input(MX6SL_ARM2_EPDC_GDSP); + gpio_direction_input(MX6SL_ARM2_EPDC_GDOE); + gpio_direction_input(MX6SL_ARM2_EPDC_GDRL); + gpio_direction_input(MX6SL_ARM2_EPDC_SDCLK); + gpio_direction_input(MX6SL_ARM2_EPDC_SDOE); + gpio_direction_input(MX6SL_ARM2_EPDC_SDLE); + gpio_direction_input(MX6SL_ARM2_EPDC_SDSHR); + gpio_direction_input(MX6SL_ARM2_EPDC_BDR0); + gpio_direction_input(MX6SL_ARM2_EPDC_SDCE0); + gpio_direction_input(MX6SL_ARM2_EPDC_SDCE1); + gpio_direction_input(MX6SL_ARM2_EPDC_SDCE2); +} + +static void epdc_disable_pins(void) +{ + /* Configure MUX settings for EPDC pins to + * GPIO and drive to 0. */ + mxc_iomux_v3_setup_multiple_pads(mx6sl_arm2_epdc_disable_pads, \ + ARRAY_SIZE(mx6sl_arm2_epdc_disable_pads)); + + gpio_direction_output(MX6SL_ARM2_EPDC_SDDO_0, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_SDDO_1, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_SDDO_2, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_SDDO_3, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_SDDO_4, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_SDDO_5, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_SDDO_6, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_SDDO_7, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_GDCLK, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_GDSP, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_GDOE, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_GDRL, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_SDCLK, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_SDOE, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_SDLE, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_SDSHR, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_BDR0, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_SDCE0, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_SDCE1, 0); + gpio_direction_output(MX6SL_ARM2_EPDC_SDCE2, 0); +} + +static struct fb_videomode e60_v110_mode = { + .name = "E60_V110", + .refresh = 50, + .xres = 800, + .yres = 600, + .pixclock = 18604700, + .left_margin = 8, + .right_margin = 178, + .upper_margin = 4, + .lower_margin = 10, + .hsync_len = 20, + .vsync_len = 4, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, +}; +static struct fb_videomode e60_v220_mode = { + .name = "E60_V220", + .refresh = 85, + .xres = 800, + .yres = 600, + .pixclock = 30000000, + .left_margin = 8, + .right_margin = 164, + .upper_margin = 4, + .lower_margin = 8, + .hsync_len = 4, + .vsync_len = 1, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, + .refresh = 85, + .xres = 800, + .yres = 600, +}; +static struct fb_videomode e060scm_mode = { + .name = "E060SCM", + .refresh = 85, + .xres = 800, + .yres = 600, + .pixclock = 26666667, + .left_margin = 8, + .right_margin = 100, + .upper_margin = 4, + .lower_margin = 8, + .hsync_len = 4, + .vsync_len = 1, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, +}; +static struct fb_videomode e97_v110_mode = { + .name = "E97_V110", + .refresh = 50, + .xres = 1200, + .yres = 825, + .pixclock = 32000000, + .left_margin = 12, + .right_margin = 128, + .upper_margin = 4, + .lower_margin = 10, + .hsync_len = 20, + .vsync_len = 4, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0, +}; + +static struct imx_epdc_fb_mode panel_modes[] = { + { + &e60_v110_mode, + 4, /* vscan_holdoff */ + 10, /* sdoed_width */ + 20, /* sdoed_delay */ + 10, /* sdoez_width */ + 20, /* sdoez_delay */ + 428, /* gdclk_hp_offs */ + 20, /* gdsp_offs */ + 0, /* gdoe_offs */ + 1, /* gdclk_offs */ + 1, /* num_ce */ + }, + { + &e60_v220_mode, + 4, /* vscan_holdoff */ + 10, /* sdoed_width */ + 20, /* sdoed_delay */ + 10, /* sdoez_width */ + 20, /* sdoez_delay */ + 465, /* gdclk_hp_offs */ + 20, /* gdsp_offs */ + 0, /* gdoe_offs */ + 9, /* gdclk_offs */ + 1, /* num_ce */ + }, + { + &e060scm_mode, + 4, /* vscan_holdoff */ + 10, /* sdoed_width */ + 20, /* sdoed_delay */ + 10, /* sdoez_width */ + 20, /* sdoez_delay */ + 419, /* gdclk_hp_offs */ + 20, /* gdsp_offs */ + 0, /* gdoe_offs */ + 5, /* gdclk_offs */ + 1, /* num_ce */ + }, + { + &e97_v110_mode, + 8, /* vscan_holdoff */ + 10, /* sdoed_width */ + 20, /* sdoed_delay */ + 10, /* sdoez_width */ + 20, /* sdoez_delay */ + 632, /* gdclk_hp_offs */ + 20, /* gdsp_offs */ + 0, /* gdoe_offs */ + 1, /* gdclk_offs */ + 3, /* num_ce */ + } +}; + +static struct imx_epdc_fb_platform_data epdc_data = { + .epdc_mode = panel_modes, + .num_modes = ARRAY_SIZE(panel_modes), + .get_pins = epdc_get_pins, + .put_pins = epdc_put_pins, + .enable_pins = epdc_enable_pins, + .disable_pins = epdc_disable_pins, +}; + static void imx6_arm2_usbotg_vbus(bool on) { if (on) @@ -262,6 +715,11 @@ static void __init mx6_arm2_init(void) gpio_request(MX6_ARM2_LCD_PWR_EN, "elcdif-power-on"); gpio_direction_output(MX6_ARM2_LCD_PWR_EN, 1); mxc_register_device(&lcd_wvga_device, NULL); + + imx6dl_add_imx_pxp(); + imx6dl_add_imx_pxp_client(); + mxc_register_device(&max17135_sensor_device, NULL); + imx6dl_add_imx_epdc(&epdc_data); } extern void __iomem *twd_base; diff --git a/arch/arm/mach-mx6/board-mx6sl_arm2.h b/arch/arm/mach-mx6/board-mx6sl_arm2.h index 29893dbcd2f8..376e7d463c7b 100755 --- a/arch/arm/mach-mx6/board-mx6sl_arm2.h +++ b/arch/arm/mach-mx6/board-mx6sl_arm2.h @@ -127,4 +127,84 @@ static iomux_v3_cfg_t mx6sl_arm2_pads[] = { MX6SL_PAD_KEY_ROW5__GPIO_4_3, }; +static iomux_v3_cfg_t mx6sl_arm2_epdc_enable_pads[] = { + /* EPDC */ + MX6SL_PAD_EPDC_D0__EPDC_SDDO_0, + MX6SL_PAD_EPDC_D1__EPDC_SDDO_1, + MX6SL_PAD_EPDC_D2__EPDC_SDDO_2, + MX6SL_PAD_EPDC_D3__EPDC_SDDO_3, + MX6SL_PAD_EPDC_D4__EPDC_SDDO_4, + MX6SL_PAD_EPDC_D5__EPDC_SDDO_5, + MX6SL_PAD_EPDC_D6__EPDC_SDDO_6, + MX6SL_PAD_EPDC_D7__EPDC_SDDO_7, + MX6SL_PAD_EPDC_D8__EPDC_SDDO_8, + MX6SL_PAD_EPDC_D9__EPDC_SDDO_9, + MX6SL_PAD_EPDC_D10__EPDC_SDDO_10, + MX6SL_PAD_EPDC_D11__EPDC_SDDO_11, + MX6SL_PAD_EPDC_D12__EPDC_SDDO_12, + MX6SL_PAD_EPDC_D13__EPDC_SDDO_13, + MX6SL_PAD_EPDC_D14__EPDC_SDDO_14, + MX6SL_PAD_EPDC_D15__EPDC_SDDO_15, + + MX6SL_PAD_EPDC_GDCLK__EPDC_GDCLK, + MX6SL_PAD_EPDC_GDSP__EPDC_GDSP, + MX6SL_PAD_EPDC_GDOE__EPDC_GDOE, + MX6SL_PAD_EPDC_GDRL__EPDC_GDRL, + MX6SL_PAD_EPDC_SDCLK__EPDC_SDCLK, + MX6SL_PAD_EPDC_SDOE__EPDC_SDOE, + MX6SL_PAD_EPDC_SDLE__EPDC_SDLE, + MX6SL_PAD_EPDC_SDSHR__EPDC_SDSHR, + MX6SL_PAD_EPDC_BDR0__EPDC_BDR_0, + MX6SL_PAD_EPDC_SDCE0__EPDC_SDCE_0, + MX6SL_PAD_EPDC_SDCE1__EPDC_SDCE_1, + MX6SL_PAD_EPDC_SDCE2__EPDC_SDCE_2, + + /* EPD PMIC (Maxim 17135) pins */ + MX6SL_PAD_EPDC_VCOM0__GPIO_2_3, + MX6SL_PAD_EPDC_PWRSTAT__GPIO_2_13, + MX6SL_PAD_EPDC_PWRCTRL0__GPIO_2_7, + MX6SL_PAD_EPDC_PWRWAKEUP__GPIO_2_14, + + MX6SL_PAD_PWM1__CCM_CLKO, +}; + +static iomux_v3_cfg_t mx6sl_arm2_epdc_disable_pads[] = { + /* EPDC */ + MX6SL_PAD_EPDC_D0__GPIO_1_7, + MX6SL_PAD_EPDC_D1__GPIO_1_8, + MX6SL_PAD_EPDC_D2__GPIO_1_9, + MX6SL_PAD_EPDC_D3__GPIO_1_10, + MX6SL_PAD_EPDC_D4__GPIO_1_11, + MX6SL_PAD_EPDC_D5__GPIO_1_12, + MX6SL_PAD_EPDC_D6__GPIO_1_13, + MX6SL_PAD_EPDC_D7__GPIO_1_14, + MX6SL_PAD_EPDC_D8__GPIO_1_15, + MX6SL_PAD_EPDC_D9__GPIO_1_16, + MX6SL_PAD_EPDC_D10__GPIO_1_17, + MX6SL_PAD_EPDC_D11__GPIO_1_18, + MX6SL_PAD_EPDC_D12__GPIO_1_19, + MX6SL_PAD_EPDC_D13__GPIO_1_20, + MX6SL_PAD_EPDC_D14__GPIO_1_21, + MX6SL_PAD_EPDC_D15__GPIO_1_22, + + MX6SL_PAD_EPDC_GDCLK__GPIO_1_31, + MX6SL_PAD_EPDC_GDSP__GPIO_2_2, + MX6SL_PAD_EPDC_GDOE__GPIO_2_0, + MX6SL_PAD_EPDC_GDRL__GPIO_2_1, + MX6SL_PAD_EPDC_SDCLK__GPIO_1_23, + MX6SL_PAD_EPDC_SDOE__GPIO_1_25, + MX6SL_PAD_EPDC_SDLE__GPIO_1_24, + MX6SL_PAD_EPDC_SDSHR__GPIO_1_26, + MX6SL_PAD_EPDC_BDR0__GPIO_2_5, + MX6SL_PAD_EPDC_SDCE0__GPIO_1_27, + MX6SL_PAD_EPDC_SDCE1__GPIO_1_28, + MX6SL_PAD_EPDC_SDCE2__GPIO_1_29, + + /* EPD PMIC (Maxim 17135) pins */ + MX6SL_PAD_EPDC_VCOM0__GPIO_2_3, + MX6SL_PAD_EPDC_PWRSTAT__GPIO_2_13, + MX6SL_PAD_EPDC_PWRCTRL0__GPIO_2_7, + MX6SL_PAD_EPDC_PWRWAKEUP__GPIO_2_14, +}; + #endif diff --git a/arch/arm/mach-mx6/clock_mx6sl.c b/arch/arm/mach-mx6/clock_mx6sl.c index ada76d716a89..20cfd922584d 100755 --- a/arch/arm/mach-mx6/clock_mx6sl.c +++ b/arch/arm/mach-mx6/clock_mx6sl.c @@ -2414,9 +2414,6 @@ static unsigned long _clk_epdc_lcdif_pix_round_rate(struct clk *clk, __calc_pre_post_dividers(1 << 3, div, &pre, &post); - printk("round_rate: parent_rate = %d, rate = %d, div = %d, pre = %d, post = %d\n", - parent_rate, rate, div, pre, post); - return parent_rate / (pre * post); } -- 2.39.5