From b25658ed7d24cd8b1f9a72148e80e216b6a0c17a Mon Sep 17 00:00:00 2001 From: =?utf8?q?J=C3=B6rg=20Krause?= Date: Fri, 13 Jan 2017 21:44:28 +0100 Subject: [PATCH] ASoC: mxs-saif: fix setting SAIF1 register MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit If SAIF0 is used in master and SAIF1 in slave mode setting the SAIF1 register in mxs_saif_set_dai_fmt() does not have any effect on the interface as the clk gate needs to be cleared before the register can be written. Signed-off-by: Jörg Krause Signed-off-by: Mark Brown --- sound/soc/mxs/mxs-saif.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/sound/soc/mxs/mxs-saif.c b/sound/soc/mxs/mxs-saif.c index a002ab892772..9012a2036131 100644 --- a/sound/soc/mxs/mxs-saif.c +++ b/sound/soc/mxs/mxs-saif.c @@ -299,6 +299,16 @@ static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) return -EBUSY; } + /* If SAIF1 is configured as slave, the clk gate needs to be cleared + * before the register can be written. + */ + if (saif->id != saif->master_id) { + __raw_writel(BM_SAIF_CTRL_SFTRST, + saif->base + SAIF_CTRL + MXS_CLR_ADDR); + __raw_writel(BM_SAIF_CTRL_CLKGATE, + saif->base + SAIF_CTRL + MXS_CLR_ADDR); + } + scr0 = __raw_readl(saif->base + SAIF_CTRL); scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \ & ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY; -- 2.39.2