From b5fb5ce97d957edee762648186161e60358ad2d5 Mon Sep 17 00:00:00 2001 From: Sandor Yu Date: Wed, 6 Jun 2012 16:39:35 +0800 Subject: [PATCH] ENGR00212529 MX6x show video to fb0 when bootup, the color space incorrect. DP CSC setting not update because incorrect DP sync flow SRM Mode. Signed-off-by: Sandor Yu --- drivers/mxc/ipu3/ipu_disp.c | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/drivers/mxc/ipu3/ipu_disp.c b/drivers/mxc/ipu3/ipu_disp.c index 706dc2160f48..680361898e8f 100644 --- a/drivers/mxc/ipu3/ipu_disp.c +++ b/drivers/mxc/ipu3/ipu_disp.c @@ -2010,16 +2010,8 @@ int32_t _ipu_disp_set_window_pos(struct ipu_soc *ipu, ipu_channel_t channel, ipu_dp_write(ipu, (x_pos << 16) | y_pos, DP_FG_POS(flow)); - if (ipu_is_channel_busy(ipu, channel)) { - /* controled by FSU if channel enabled */ - reg = ipu_cm_read(ipu, IPU_SRM_PRI2) & (~(0x3 << dp_srm_shift)); - reg |= (0x1 << dp_srm_shift); - ipu_cm_write(ipu, reg, IPU_SRM_PRI2); - } else { - /* disable auto swap, controled by MCU if channel disabled */ - reg = ipu_cm_read(ipu, IPU_SRM_PRI2) & (~(0x3 << dp_srm_shift)); - ipu_cm_write(ipu, reg, IPU_SRM_PRI2); - } + reg = ipu_cm_read(ipu, IPU_SRM_PRI2) | 0x8; + ipu_cm_write(ipu, reg, IPU_SRM_PRI2); return 0; } -- 2.39.5