From b98eba52784fbd4a96241c5395c2c8d99fdb9433 Mon Sep 17 00:00:00 2001 From: Eddie Wai Date: Mon, 17 May 2010 17:32:56 -0700 Subject: [PATCH] bnx2: Fix register printouts during NETEV_WATCHDOG. Dump the correct MCP registers and add EMAC_RX_STATUS register during NETDEV_WATCHDOG for debugging. Signed-off-by: Eddie Wai Signed-off-by: Benjamin Li Signed-off-by: Michael Chan Signed-off-by: David S. Miller --- drivers/net/bnx2.c | 15 ++++++++++++--- drivers/net/bnx2.h | 2 ++ 2 files changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c index 667f4196dc29..c281218f6d5e 100644 --- a/drivers/net/bnx2.c +++ b/drivers/net/bnx2.c @@ -6301,14 +6301,23 @@ static void bnx2_dump_state(struct bnx2 *bp) { struct net_device *dev = bp->dev; + u32 mcp_p0, mcp_p1; netdev_err(dev, "DEBUG: intr_sem[%x]\n", atomic_read(&bp->intr_sem)); - netdev_err(dev, "DEBUG: EMAC_TX_STATUS[%08x] RPM_MGMT_PKT_CTRL[%08x]\n", + netdev_err(dev, "DEBUG: EMAC_TX_STATUS[%08x] EMAC_RX_STATUS[%08x]\n", REG_RD(bp, BNX2_EMAC_TX_STATUS), + REG_RD(bp, BNX2_EMAC_RX_STATUS)); + netdev_err(dev, "DEBUG: RPM_MGMT_PKT_CTRL[%08x]\n", REG_RD(bp, BNX2_RPM_MGMT_PKT_CTRL)); + if (CHIP_NUM(bp) == CHIP_NUM_5709) { + mcp_p0 = BNX2_MCP_STATE_P0; + mcp_p1 = BNX2_MCP_STATE_P1; + } else { + mcp_p0 = BNX2_MCP_STATE_P0_5708; + mcp_p1 = BNX2_MCP_STATE_P1_5708; + } netdev_err(dev, "DEBUG: MCP_STATE_P0[%08x] MCP_STATE_P1[%08x]\n", - bnx2_reg_rd_ind(bp, BNX2_MCP_STATE_P0), - bnx2_reg_rd_ind(bp, BNX2_MCP_STATE_P1)); + bnx2_reg_rd_ind(bp, mcp_p0), bnx2_reg_rd_ind(bp, mcp_p1)); netdev_err(dev, "DEBUG: HC_STATS_INTERRUPT_STATUS[%08x]\n", REG_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS)); if (bp->flags & BNX2_FLAG_USING_MSIX) diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h index dd35bd0b7e05..ddaa3fc99876 100644 --- a/drivers/net/bnx2.h +++ b/drivers/net/bnx2.h @@ -6347,6 +6347,8 @@ struct l2_fhdr { #define BNX2_MCP_SCRATCH 0x00160000 #define BNX2_MCP_STATE_P1 0x0016f9c8 #define BNX2_MCP_STATE_P0 0x0016fdc8 +#define BNX2_MCP_STATE_P1_5708 0x001699c8 +#define BNX2_MCP_STATE_P0_5708 0x00169dc8 #define BNX2_SHM_HDR_SIGNATURE BNX2_MCP_SCRATCH #define BNX2_SHM_HDR_SIGNATURE_SIG_MASK 0xffff0000 -- 2.39.5