From ba6f7011bde0ba762f89e7c544d1e0f24dc1bd4e Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 31 Mar 2017 13:20:45 +0900 Subject: [PATCH] arm64: dts: uniphier: add input-delay properties to Cadence eMMC node Since commit a89c472d8b55 ("mmc: sdhci-cadence: Update PHY delay configuration"), PHY parameters must be specified by DT. The hard-coded settings have been converted as follows: - SDHCI_CDNS_PHY_DLY_SD_DEFAULT -> cdns,phy-input-delay-legacy - SDHCI_CDNS_PHY_DLY_EMMC_SDR -> cdns,phy-input-delay-mmc-highspeed - SDHCI_CDNS_PHY_DLY_EMMC_DDR -> cdns,phy-input-delay-mmc-ddr The following have not been moved: - SDHCI_CDNS_PHY_DLY_SD_HS this is unneeded in the eMMC configuration - SDHCI_CDNS_PHY_DLY_EMMC_LEGACY this is never enabled by the driver as it is covered by SDHCI_CDNS_PHY_DLY_SD_DEFAULT Signed-off-by: Masahiro Yamada --- arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 3 +++ arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 3 +++ 2 files changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi index 151c043b4835..42f1803cce18 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi @@ -310,6 +310,9 @@ bus-width = <8>; mmc-ddr-1_8v; mmc-hs200-1_8v; + cdns,phy-input-delay-legacy = <4>; + cdns,phy-input-delay-mmc-highspeed = <2>; + cdns,phy-input-delay-mmc-ddr = <3>; }; usb0: usb@5a800100 { diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi index 6193f11acb78..e4499ff37d51 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi @@ -384,6 +384,9 @@ bus-width = <8>; mmc-ddr-1_8v; mmc-hs200-1_8v; + cdns,phy-input-delay-legacy = <4>; + cdns,phy-input-delay-mmc-highspeed = <2>; + cdns,phy-input-delay-mmc-ddr = <3>; }; soc-glue@5f800000 { -- 2.39.2