From bc27b7d3f096e88f9b6571965452925fc93f2ca3 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Thu, 12 Mar 2015 17:10:35 +0200 Subject: [PATCH] drm/i915: Use DP_LINK_RATE_SET whenever possible MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Drop the gen9 checks from the code and issue DP_LINK_RATE_SET whenever the sink reports to support it. Signed-off-by: Ville Syrjälä Reviewed-by: Sonika Jindal Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_dp.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 5d8ec3a33502..aa3c6781b65c 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1371,14 +1371,15 @@ found: intel_dp->lane_count = lane_count; - intel_dp->link_bw = - drm_dp_link_rate_to_bw_code(supported_rates[clock]); - - if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) { + if (intel_dp->num_supported_rates) { + intel_dp->link_bw = 0; intel_dp->rate_select = rate_to_index(supported_rates[clock], intel_dp->supported_rates); - intel_dp->link_bw = 0; + } else { + intel_dp->link_bw = + drm_dp_link_rate_to_bw_code(supported_rates[clock]); + intel_dp->rate_select = 0; } pipe_config->pipe_bpp = bpp; @@ -3492,7 +3493,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp) if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2); - if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) + if (intel_dp->num_supported_rates) drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET, &intel_dp->rate_select, 1); -- 2.39.5