From c4b7586fe29db1085db3de95c0ee17222136374b Mon Sep 17 00:00:00 2001 From: John Crispin Date: Tue, 24 Jul 2012 08:29:46 +0200 Subject: [PATCH] MIPS: Lantiq: Add helper to set PCI clock delay The PCI core has a register that allows us to set the nanosecond delay of the PCI clock lane. This patch adds a helper function to allow setting this value. Signed-off-by: John Crispin Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4119/ Signed-off-by: Ralf Baechle --- .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 +++ arch/mips/lantiq/xway/sysctrl.c | 14 ++++++++++++++ 2 files changed, 17 insertions(+) diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h index 6a2df709c576..1de5d826c49e 100644 --- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h @@ -87,5 +87,8 @@ extern __iomem void *ltq_cgu_membase; extern void ltq_pmu_enable(unsigned int module); extern void ltq_pmu_disable(unsigned int module); +/* allow pci driver to set the pci clk delay */ +void ltq_pci_set_delay(u8 delay); + #endif /* CONFIG_SOC_TYPE_XWAY */ #endif /* _LTQ_XWAY_H__ */ diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c index befbb760ab76..79887aff48da 100644 --- a/arch/mips/lantiq/xway/sysctrl.c +++ b/arch/mips/lantiq/xway/sysctrl.c @@ -41,6 +41,10 @@ /* power status register */ #define PWDSR(x) ((x) ? (PMU_PWDSR1) : (PMU_PWDSR)) +/* pci delay is 6 bit wide and 18 bit into the register*/ +#define PCI_DLY_MASK 0x3f +#define PCI_DLY_SHIFT 18 + /* clock gates that we can en/disable */ #define PMU_USB0_P BIT(0) #define PMU_PCI BIT(4) @@ -258,6 +262,16 @@ static void clkdev_add_pci(void) clkdev_add(&clk_ext->cl); } +/* allow PCI driver to specify the clock delay. This is a 6 bit value */ +void ltq_pci_set_delay(u8 delay) +{ + u32 val = ltq_cgu_r32(pcicr); + + val &= ~(PCI_DLY_MASK << PCI_DLY_SHIFT); + val |= ((u32)(delay & PCI_DLY_MASK)) << PCI_DLY_SHIFT; + ltq_cgu_w32(val, pcicr); +} + /* xway socs can generate clocks on gpio pins */ static unsigned long valid_clkout_rates[4][5] = { {CLOCK_32_768K, CLOCK_1_536M, CLOCK_2_5M, CLOCK_12M, 0}, -- 2.39.5