From cb0bd8211aa6e959bff5197a083e32fca4752353 Mon Sep 17 00:00:00 2001 From: Ranjani Vaidyanathan Date: Fri, 16 Aug 2013 12:20:16 -0500 Subject: [PATCH] ENGR00273792-2 ARM:iMX6x: Improve CPUFREQ driver. 1. Add support for VDDSOC/VDDPU operating points that track the VDDARM_CAP within 50mV to the device tree. 2. Add CPU freq and VDDSOC/VDDPU operating points to MX6DL and MX6SL. Signed-off-by: Ranjani Vaidyanathan --- arch/arm/boot/dts/imx6dl.dtsi | 20 ++++++++++++++++++++ arch/arm/boot/dts/imx6q.dtsi | 7 +++++++ arch/arm/boot/dts/imx6sl.dtsi | 20 ++++++++++++++++++++ 3 files changed, 47 insertions(+) diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index 0c5d63d460fb..2399c40a54d8 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -21,6 +21,26 @@ device_type = "cpu"; reg = <0>; next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 996000 1250000 + 792000 1175000 + 396000 1075000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1175000 + 792000 1175000 + 396000 1175000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks 104>, <&clks 6>, <&clks 16>, + <&clks 17>, <&clks 170>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; }; cpu@1 { diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index e9d6b08ed871..d3adfbb5417b 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -32,6 +32,13 @@ 792000 1150000 396000 950000 >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 1200000 1275000 + 996000 1250000 + 792000 1175000 + 396000 1175000 + >; clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clks 104>, <&clks 6>, <&clks 16>, <&clks 17>, <&clks 170>; diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index b2b702e0f85f..57747a8b9bd1 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -34,6 +34,26 @@ device_type = "cpu"; reg = <0x0>; next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 996000 1250000 + 792000 1150000 + 396000 950000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1200000 + 792000 1150000 + 396000 1150000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks 104>, <&clks 6>, <&clks 16>, + <&clks 17>, <&clks 170>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; }; }; -- 2.39.5