From cd78d0cd63ebce518b5c342fe6ef1f4613bb039d Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Thu, 9 Oct 2014 21:50:30 -0700 Subject: [PATCH] ARM: dts: rockchip: enable init rate for clock We need to initialize PLL rate and some of bus clock rate while kernel init, for there is no other module will do that. Basically on rk3288 we use GPLL for cpu bus, peripheral bus and most of peripheral clock, CPLL for devices who require 50M/200M clock rate, leave NPLL behind for special requirement from display system. The common-clock-framework will help us to select best source for child clocks after we init the PLLs propriety. Signed-off-by: Kever Yang Reviewed-by: Doug Anderson Tested-by: Doug Anderson Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index cb18bb457568..b53e833e5667 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -472,6 +472,16 @@ rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; + assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, + <&cru PLL_NPLL>, <&cru ACLK_CPU>, + <&cru HCLK_CPU>, <&cru PCLK_CPU>, + <&cru ACLK_PERI>, <&cru HCLK_PERI>, + <&cru PCLK_PERI>; + assigned-clock-rates = <594000000>, <400000000>, + <500000000>, <300000000>, + <150000000>, <75000000>, + <300000000>, <150000000>, + <75000000>; }; grf: syscon@ff770000 { -- 2.39.5