From cd9d11820f4232856d6254a29fbb9c4f51a981c2 Mon Sep 17 00:00:00 2001 From: Ezequiel Garcia Date: Mon, 12 Aug 2013 14:14:48 -0300 Subject: [PATCH] mtd: nand: pxa3xx: Handle ECC and DMA enable/disable properly When ECC is not selected, the ECC enable bit must be cleared in the NAND control register. Same applies to DMA. Signed-off-by: Ezequiel Garcia Tested-by: Daniel Mack Signed-off-by: Brian Norris Signed-off-by: David Woodhouse --- drivers/mtd/nand/pxa3xx_nand.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index c4bff66ef267..1dcda6badfdc 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -314,8 +314,17 @@ static void pxa3xx_nand_start(struct pxa3xx_nand_info *info) uint32_t ndcr; ndcr = host->reg_ndcr; - ndcr |= info->use_ecc ? NDCR_ECC_EN : 0; - ndcr |= info->use_dma ? NDCR_DMA_EN : 0; + + if (info->use_ecc) + ndcr |= NDCR_ECC_EN; + else + ndcr &= ~NDCR_ECC_EN; + + if (info->use_dma) + ndcr |= NDCR_DMA_EN; + else + ndcr &= ~NDCR_DMA_EN; + ndcr |= NDCR_ND_RUN; /* clear status bits and run */ -- 2.39.5