From cf532bb255920202b6483914b0e19a55f0067729 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Wed, 4 Sep 2013 18:30:02 +0300 Subject: [PATCH] drm/i915: Move double wide mode handling into pipe_config MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Determine the need for double wide mode already in compute_config stage as we need that information to figure out if horizontal coordinates need to be adjusted. Signed-off-by: Ville Syrjälä Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_display.c | 31 ++++++++++++++++++---------- drivers/gpu/drm/i915/intel_drv.h | 2 ++ 2 files changed, 22 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 15f78ffb93be..94c85214daf4 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4143,6 +4143,23 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, struct drm_device *dev = crtc->base.dev; struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; + if (INTEL_INFO(dev)->gen < 4) { + struct drm_i915_private *dev_priv = dev->dev_private; + int clock_limit = + dev_priv->display.get_display_clock_speed(dev); + + /* + * Enable pixel doubling when the dot clock + * is > 90% of the (display) core speed. + * + * XXX: No double-wide on 915GM pipe B. Is that + * the only reason for the pipe == PIPE_A check? + */ + if (crtc->pipe == PIPE_A && + adjusted_mode->clock > clock_limit * 9 / 10) + pipe_config->double_wide = true; + } + /* Cantiga+ cannot handle modes with a hsync front porch of 0. * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. */ @@ -4801,17 +4818,8 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) pipeconf = 0; - if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) { - /* Enable pixel doubling when the dot clock is > 90% of the (display) - * core speed. - * - * XXX: No double-wide on 915GM pipe B. Is that the only reason for the - * pipe == 0 check? - */ - if (intel_crtc->config.adjusted_mode.clock > - dev_priv->display.get_display_clock_speed(dev) * 9 / 10) - pipeconf |= PIPECONF_DOUBLE_WIDE; - } + if (intel_crtc->config.double_wide) + pipeconf |= PIPECONF_DOUBLE_WIDE; /* only g4x and later have fancy bpc/dither controls */ if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { @@ -8336,6 +8344,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc, pipe_config->pch_pfit.pos, pipe_config->pch_pfit.size); DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); + DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); } static bool check_encoder_cloning(struct drm_crtc *crtc) diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 821e19adb15c..b85354f9440b 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -305,6 +305,8 @@ struct intel_crtc_config { struct intel_link_m_n fdi_m_n; bool ips_enabled; + + bool double_wide; }; struct intel_crtc { -- 2.39.5