From df33acf4c684119ab9882e5f29e49d5f29060df5 Mon Sep 17 00:00:00 2001 From: Ram Pai Date: Sun, 6 Nov 2011 10:33:57 +0800 Subject: [PATCH] PCI: delay configuration of SRIOV capability The SRIOV capability, namely page size and total_vfs of a device are configured during enumeration phase of the device. This can potentially interfere with the PCI operations of the platform, if the IOV capability of the device is not enabled. The following patch postpones the configuration of the IOV capability of the device to a later point, when the IOV capability is explicitly enabled by the device driver. The patch is tested on x86 and power platform. Tested-by: Donald Dutile Signed-off-by: Ram Pai Signed-off-by: Jesse Barnes --- drivers/pci/iov.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c index 6a4d70386a3d..0321fa3b4226 100644 --- a/drivers/pci/iov.c +++ b/drivers/pci/iov.c @@ -347,6 +347,8 @@ static int sriov_enable(struct pci_dev *dev, int nr_virtfn) return rc; } + pci_write_config_dword(dev, iov->pos + PCI_SRIOV_SYS_PGSIZE, iov->pgsz); + iov->ctrl |= PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE; pci_cfg_access_lock(dev); pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl); @@ -452,7 +454,6 @@ static int sriov_init(struct pci_dev *dev, int pos) found: pci_write_config_word(dev, pos + PCI_SRIOV_CTRL, ctrl); - pci_write_config_word(dev, pos + PCI_SRIOV_NUM_VF, total); pci_read_config_word(dev, pos + PCI_SRIOV_VF_OFFSET, &offset); pci_read_config_word(dev, pos + PCI_SRIOV_VF_STRIDE, &stride); if (!offset || (total > 1 && !stride)) @@ -465,7 +466,6 @@ found: return -EIO; pgsz &= ~(pgsz - 1); - pci_write_config_dword(dev, pos + PCI_SRIOV_SYS_PGSIZE, pgsz); nres = 0; for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) { -- 2.39.5