From e2127487b8cf1368b9a598f135f5be004e1ba98c Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Tue, 17 Apr 2012 10:24:50 +0800 Subject: [PATCH] ENGR00180230 MX6 PCIE: enlarge the eye diagram and force to GEN1 * Adjust the parameters, enlarge the eye diagram. * Force to the PCIE GEN1 speed. Signed-off-by: Richard Zhu --- arch/arm/mach-mx6/pcie.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-mx6/pcie.c b/arch/arm/mach-mx6/pcie.c index 3fcb115df95c..38e9abcd29cc 100644 --- a/arch/arm/mach-mx6/pcie.c +++ b/arch/arm/mach-mx6/pcie.c @@ -696,11 +696,11 @@ static int __devinit imx_pcie_pltfm_probe(struct platform_device *pdev) IOMUXC_GPR12); imx_pcie_clrset(iomuxc_gpr12_los_level, 9 << 4, IOMUXC_GPR12); - imx_pcie_clrset(iomuxc_gpr8_tx_deemph_gen1, 21 << 0, IOMUXC_GPR8); - imx_pcie_clrset(iomuxc_gpr8_tx_deemph_gen2_3p5db, 21 << 6, IOMUXC_GPR8); - imx_pcie_clrset(iomuxc_gpr8_tx_deemph_gen2_6db, 32 << 12, IOMUXC_GPR8); - imx_pcie_clrset(iomuxc_gpr8_tx_swing_full, 115 << 18, IOMUXC_GPR8); - imx_pcie_clrset(iomuxc_gpr8_tx_swing_low, 115 << 25, IOMUXC_GPR8); + imx_pcie_clrset(iomuxc_gpr8_tx_deemph_gen1, 0 << 0, IOMUXC_GPR8); + imx_pcie_clrset(iomuxc_gpr8_tx_deemph_gen2_3p5db, 0 << 6, IOMUXC_GPR8); + imx_pcie_clrset(iomuxc_gpr8_tx_deemph_gen2_6db, 0 << 12, IOMUXC_GPR8); + imx_pcie_clrset(iomuxc_gpr8_tx_swing_full, 127 << 18, IOMUXC_GPR8); + imx_pcie_clrset(iomuxc_gpr8_tx_swing_low, 127 << 25, IOMUXC_GPR8); /* Enable the pwr, clks and so on */ imx_pcie_enable_controller(dev); @@ -714,6 +714,13 @@ static int __devinit imx_pcie_pltfm_probe(struct platform_device *pdev) imx_pcie_regions_setup(dbi_base); usleep_range(3000, 4000); + /* + * Force to GEN1 because of PCIE2USB storage stress tests + * would be failed when GEN2 is enabled + */ + writel(((readl(dbi_base + LNK_CAP) & 0xfffffff0) | 0x1), + dbi_base + LNK_CAP); + /* start link up */ imx_pcie_clrset(iomuxc_gpr12_app_ltssm_enable, 1 << 10, IOMUXC_GPR12); -- 2.39.5