From e370df16bc2084b79a548479e0ea1265b8352b42 Mon Sep 17 00:00:00 2001 From: Leonid Yegoshin Date: Thu, 14 Nov 2013 16:12:29 +0000 Subject: [PATCH] MIPS: Add function for flushing the TLB using the TLBINV instruction Signed-off-by: Leonid Yegoshin Signed-off-by: Markos Chandras Acked-by: John Crispin Patchwork: http://patchwork.linux-mips.org/patch/6136/ --- arch/mips/include/asm/mipsregs.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 0558f9b429ae..d9910a1e754a 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -704,6 +704,19 @@ static inline int mm_insn_16bit(u16 insn) return (opcode >= 1 && opcode <= 3) ? 1 : 0; } +/* + * TLB Invalidate Flush + */ +static inline void tlbinvf(void) +{ + __asm__ __volatile__( + ".set push\n\t" + ".set noreorder\n\t" + ".word 0x42000004\n\t" /* tlbinvf */ + ".set pop"); +} + + /* * Functions to access the R10000 performance counters. These are basically * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit -- 2.39.5