From e381c552d5528b1b39affc8ddc5adb9de3bc7bc1 Mon Sep 17 00:00:00 2001 From: Jason Liu Date: Tue, 7 Feb 2012 13:56:02 +0800 Subject: [PATCH] ENGR00173869-2: i.mx6: add the i.mx6dl memory map and irq definion i.mx6dl shares with almost the same memory layout with i.mx6d/q except it adds some new fetures such as pxp/epdc etc. Signed-off-by: Jason Liu --- arch/arm/plat-mxc/include/mach/mx6.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/plat-mxc/include/mach/mx6.h b/arch/arm/plat-mxc/include/mach/mx6.h index 61296199ee6a..c60a84034990 100644 --- a/arch/arm/plat-mxc/include/mach/mx6.h +++ b/arch/arm/plat-mxc/include/mach/mx6.h @@ -75,6 +75,7 @@ #define MX6Q_IRAM_BASE_ADDR IRAM_BASE_ADDR /* The last 4K is for cpu hotplug to workaround wdog issue*/ #define MX6Q_IRAM_SIZE (SZ_256K - SZ_4K) +#define MX6DL_IRAM_SIZE (SZ_128K - SZ_4K) /* Blocks connected via pl301periph */ #define ROMCP_ARB_BASE_ADDR 0x00000000 @@ -182,6 +183,9 @@ #define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) #define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) #define MX6Q_SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) +#define MX6DL_PXP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000) +#define MX6DL_EPDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000) +#define MX6DL_LCDIF_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000) #define MX6Q_DVFSCORE_BASE_ADDR (GPC_BASE_ADDR + 0x180) /* ATZ#2- On Platform */ @@ -231,6 +235,7 @@ #define UART3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x6C000) #define UART4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x70000) #define UART5_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x74000) +#define MX6DL_I2C4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) /* Cortex-A9 MPCore private memory region */ #define ARM_PERIPHBASE 0x00A00000 @@ -320,10 +325,12 @@ #define MX6Q_INT_ECSPI3 65 #define MX6Q_INT_ECSPI4 66 #define MX6Q_INT_ECSPI5 67 +#define MX6DL_INT_I2C4 67 #define MX6Q_INT_I2C1 68 #define MX6Q_INT_I2C2 69 #define MX6Q_INT_I2C3 70 #define MX6Q_INT_SATA 71 +#define MX6DL_INT_LCDIF 71 #define MX6Q_INT_USB_HS1 72 #define MX6Q_INT_USB_HS2 73 #define MX6Q_INT_USB_HS3 74 @@ -387,6 +394,8 @@ #define MXC_INT_CHEETAH_PERFORM 126 #define MXC_INT_CHEETAH_TRIGGER 127 #define MXC_INT_SRC_CPU_WDOG 128 +#define MX6DL_INT_EPDC 129 +#define MX6DL_INT_PXP 130 #define MXC_INT_INTERRUPT_131_NUM 131 #define MXC_INT_CSI_INTR1 132 #define MXC_INT_CSI_INTR2 133 -- 2.39.5