From ec30756507944c6c8334aa1a9768e6f13e2e6bcd Mon Sep 17 00:00:00 2001 From: Allen Xu Date: Thu, 19 Apr 2012 14:26:16 +0800 Subject: [PATCH] ENGR00180231 mx6q arm2 ONFI NAND clock change change clock source to enfc clock on mx6q arm2 lpddr board for ONFI nand when enable ddr mode Signed-off-by: Allen Xu --- drivers/mtd/nand/gpmi-nand/gpmi-lib.c | 28 +++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c index 1c273e4eb2b4..75c2e618b28a 100644 --- a/drivers/mtd/nand/gpmi-nand/gpmi-lib.c +++ b/drivers/mtd/nand/gpmi-nand/gpmi-lib.c @@ -152,7 +152,7 @@ static int enable_ddr_onfi(struct gpmi_nand_data *this) struct mtd_info *mtd = &this->mtd; int saved_chip_number = 0; uint8_t device_feature[FEATURE_SIZE]; - int mode = 0;/* there is 5 mode available, default is 0 */ + int mode = 5;/* there is 5 mode available, default is 0 */ saved_chip_number = this->current_chip; nand->select_chip(mtd, 0); @@ -178,14 +178,16 @@ static int enable_ddr_onfi(struct gpmi_nand_data *this) /* [3] about the clock, pay attention! */ nand->select_chip(mtd, saved_chip_number); { - struct clk *pll1; - pll1 = clk_get(NULL, "pll1_main_clk"); - if (IS_ERR(pll1)) { - printk(KERN_INFO "No PLL1 clock\n"); + struct clk *enfc_clk; + enfc_clk = clk_get(NULL, "enfc_clk"); + if (IS_ERR(enfc_clk)) { + printk(KERN_INFO "No enfc_clk clock\n"); return -EINVAL; } - clk_set_parent(resources->clock, pll1); - clk_set_rate(resources->clock, 20000000); + clk_set_parent(resources->clock, enfc_clk); + clk_set_rate(enfc_clk, \ + enfc_clk->round_rate(enfc_clk, 100000000)); + clk_set_rate(resources->clock, 100000000); } nand->select_chip(mtd, 0); @@ -258,18 +260,20 @@ static int enable_ddr_toggle(struct gpmi_nand_data *this) /* [3] about the clock, pay attention! */ nand->select_chip(mtd, saved_chip_number); { - struct clk *pll1; + struct clk *enfc_clk; unsigned long rate; - pll1 = clk_get(NULL, "pll1_main_clk"); - if (IS_ERR(pll1)) { - printk(KERN_INFO "No PLL1 clock\n"); + enfc_clk = clk_get(NULL, "enfc_clk"); + if (IS_ERR(enfc_clk)) { + printk(KERN_INFO "No enfc_clk clock\n"); return -EINVAL; } /* toggle nand : 133/66 MHz */ rate = 33000000; - clk_set_parent(resources->clock, pll1); + clk_set_parent(resources->clock, enfc_clk); + clk_set_rate(enfc_clk, \ + enfc_clk->round_rate(enfc_clk, rate)); clk_set_rate(resources->clock, rate); } nand->select_chip(mtd, 0); -- 2.39.5