From ec884f74f1ec8ffa6a77a2769087117aeec80c1f Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Fri, 9 Dec 2016 17:13:08 +1000 Subject: [PATCH] drm/nouveau/fifo/gf100-: recover from host mmu faults This has been on the TODO list for a while now, recovering from things such as attempting to execute a push buffer or touch a semaphore in an unmapped memory area. The only thing required on the HW side here is that the offending channel is removed from the runlist, and *not* a full reset of PFIFO. This used to be a bit messier to handle before the rework to make use of engine topology info, but is apparently now trivial. Signed-off-by: Ben Skeggs --- .../gpu/drm/nouveau/nvkm/engine/fifo/gf100.c | 3 ++- .../gpu/drm/nouveau/nvkm/engine/fifo/gk104.c | 16 +++++++------- .../gpu/drm/nouveau/nvkm/engine/fifo/gm107.c | 16 +++++++------- .../gpu/drm/nouveau/nvkm/engine/fifo/gp100.c | 22 +++++++++---------- 4 files changed, 29 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c index 352a0baec84d..ec68ea9747d5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c @@ -180,7 +180,8 @@ gf100_fifo_recover(struct gf100_fifo *fifo, struct nvkm_engine *engine, list_del_init(&chan->head); chan->killed = true; - fifo->recover.mask |= 1ULL << engine->subdev.index; + if (engine != &fifo->base.engine) + fifo->recover.mask |= 1ULL << engine->subdev.index; schedule_work(&fifo->recover.work); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c index 103c0afaaa6d..38c0910722c0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c @@ -743,14 +743,14 @@ gk104_fifo_fault_engine[] = { { 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR }, { 0x05, "BAR2", NULL, NVKM_SUBDEV_INSTMEM }, { 0x06, "SCHED" }, - { 0x07, "HOST0" }, - { 0x08, "HOST1" }, - { 0x09, "HOST2" }, - { 0x0a, "HOST3" }, - { 0x0b, "HOST4" }, - { 0x0c, "HOST5" }, - { 0x0d, "HOST6" }, - { 0x0e, "HOST7" }, + { 0x07, "HOST0", NULL, NVKM_ENGINE_FIFO }, + { 0x08, "HOST1", NULL, NVKM_ENGINE_FIFO }, + { 0x09, "HOST2", NULL, NVKM_ENGINE_FIFO }, + { 0x0a, "HOST3", NULL, NVKM_ENGINE_FIFO }, + { 0x0b, "HOST4", NULL, NVKM_ENGINE_FIFO }, + { 0x0c, "HOST5", NULL, NVKM_ENGINE_FIFO }, + { 0x0d, "HOST6", NULL, NVKM_ENGINE_FIFO }, + { 0x0e, "HOST7", NULL, NVKM_ENGINE_FIFO }, { 0x0f, "HOSTSR" }, { 0x10, "MSVLD", NULL, NVKM_ENGINE_MSVLD }, { 0x11, "MSPPP", NULL, NVKM_ENGINE_MSPPP }, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c index bd1ff877aa06..29c080683b32 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c @@ -32,14 +32,14 @@ gm107_fifo_fault_engine[] = { { 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR }, { 0x05, "BAR2", NULL, NVKM_SUBDEV_INSTMEM }, { 0x06, "SCHED" }, - { 0x07, "HOST0" }, - { 0x08, "HOST1" }, - { 0x09, "HOST2" }, - { 0x0a, "HOST3" }, - { 0x0b, "HOST4" }, - { 0x0c, "HOST5" }, - { 0x0d, "HOST6" }, - { 0x0e, "HOST7" }, + { 0x07, "HOST0", NULL, NVKM_ENGINE_FIFO }, + { 0x08, "HOST1", NULL, NVKM_ENGINE_FIFO }, + { 0x09, "HOST2", NULL, NVKM_ENGINE_FIFO }, + { 0x0a, "HOST3", NULL, NVKM_ENGINE_FIFO }, + { 0x0b, "HOST4", NULL, NVKM_ENGINE_FIFO }, + { 0x0c, "HOST5", NULL, NVKM_ENGINE_FIFO }, + { 0x0d, "HOST6", NULL, NVKM_ENGINE_FIFO }, + { 0x0e, "HOST7", NULL, NVKM_ENGINE_FIFO }, { 0x0f, "HOSTSR" }, { 0x13, "PERF" }, { 0x17, "PMU" }, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp100.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp100.c index eff83f7fb705..b2635aea9f6e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp100.c @@ -30,17 +30,17 @@ gp100_fifo_fault_engine[] = { { 0x03, "IFB", NULL, NVKM_ENGINE_IFB }, { 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR }, { 0x05, "BAR2", NULL, NVKM_SUBDEV_INSTMEM }, - { 0x06, "HOST0" }, - { 0x07, "HOST1" }, - { 0x08, "HOST2" }, - { 0x09, "HOST3" }, - { 0x0a, "HOST4" }, - { 0x0b, "HOST5" }, - { 0x0c, "HOST6" }, - { 0x0d, "HOST7" }, - { 0x0e, "HOST8" }, - { 0x0f, "HOST9" }, - { 0x10, "HOST10" }, + { 0x06, "HOST0", NULL, NVKM_ENGINE_FIFO }, + { 0x07, "HOST1", NULL, NVKM_ENGINE_FIFO }, + { 0x08, "HOST2", NULL, NVKM_ENGINE_FIFO }, + { 0x09, "HOST3", NULL, NVKM_ENGINE_FIFO }, + { 0x0a, "HOST4", NULL, NVKM_ENGINE_FIFO }, + { 0x0b, "HOST5", NULL, NVKM_ENGINE_FIFO }, + { 0x0c, "HOST6", NULL, NVKM_ENGINE_FIFO }, + { 0x0d, "HOST7", NULL, NVKM_ENGINE_FIFO }, + { 0x0e, "HOST8", NULL, NVKM_ENGINE_FIFO }, + { 0x0f, "HOST9", NULL, NVKM_ENGINE_FIFO }, + { 0x10, "HOST10", NULL, NVKM_ENGINE_FIFO }, { 0x13, "PERF" }, { 0x17, "PMU" }, { 0x18, "PTP" }, -- 2.39.5