From eccf7e8ad28e64401519e49f56abc7c799f809b5 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 14 Jan 2015 10:09:24 +1000 Subject: [PATCH] drm/nouveau/msvld: separate from bsp Switch to NVIDIA's name for the device. The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvif/class.h | 3 +- .../drm/nouveau/include/nvkm/core/device.h | 1 + .../gpu/drm/nouveau/include/nvkm/engine/bsp.h | 5 --- .../drm/nouveau/include/nvkm/engine/msvld.h | 6 +++ drivers/gpu/drm/nouveau/nvkm/engine/Kbuild | 1 + .../gpu/drm/nouveau/nvkm/engine/bsp/Kbuild | 3 -- .../gpu/drm/nouveau/nvkm/engine/device/base.c | 1 + .../drm/nouveau/nvkm/engine/device/gm100.c | 5 ++- .../gpu/drm/nouveau/nvkm/engine/device/nv50.c | 15 ++++---- .../gpu/drm/nouveau/nvkm/engine/device/nvc0.c | 19 +++++----- .../gpu/drm/nouveau/nvkm/engine/device/nve0.c | 15 ++++---- .../gpu/drm/nouveau/nvkm/engine/fifo/nv84.c | 11 ++++-- .../gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c | 16 ++++---- .../gpu/drm/nouveau/nvkm/engine/fifo/nve0.c | 10 ++--- .../gpu/drm/nouveau/nvkm/engine/msvld/Kbuild | 3 ++ .../nouveau/nvkm/engine/{bsp => msvld}/nv98.c | 38 +++++++++---------- .../nouveau/nvkm/engine/{bsp => msvld}/nvc0.c | 38 +++++++++---------- .../nouveau/nvkm/engine/{bsp => msvld}/nve0.c | 38 +++++++++---------- .../drm/nouveau/nvkm/subdev/devinit/nv98.c | 4 +- .../drm/nouveau/nvkm/subdev/devinit/nva3.c | 2 +- .../drm/nouveau/nvkm/subdev/devinit/nvaf.c | 2 +- .../drm/nouveau/nvkm/subdev/devinit/nvc0.c | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c | 3 ++ drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c | 2 +- .../gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c | 3 +- 26 files changed, 133 insertions(+), 115 deletions(-) create mode 100644 drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/msvld/Kbuild rename drivers/gpu/drm/nouveau/nvkm/engine/{bsp => msvld}/nv98.c (81%) rename drivers/gpu/drm/nouveau/nvkm/engine/{bsp => msvld}/nvc0.c (81%) rename drivers/gpu/drm/nouveau/nvkm/engine/{bsp => msvld}/nve0.c (81%) diff --git a/drivers/gpu/drm/nouveau/include/nvif/class.h b/drivers/gpu/drm/nouveau/include/nvif/class.h index 4e308eacb27a..6ed8ecca8dbf 100644 --- a/drivers/gpu/drm/nouveau/include/nvif/class.h +++ b/drivers/gpu/drm/nouveau/include/nvif/class.h @@ -134,6 +134,7 @@ struct nv_device_v0 { #define NV_DEVICE_V0_DISABLE_VIC 0x0000020000000000ULL #define NV_DEVICE_V0_DISABLE_VENC 0x0000040000000000ULL #define NV_DEVICE_V0_DISABLE_COPY2 0x0000080000000000ULL +#define NV_DEVICE_V0_DISABLE_MSVLD 0x0000100000000000ULL __u64 disable; /* disable particular subsystems */ __u64 debug0; /* as above, but *internal* ids, and *NOT* ABI */ }; @@ -348,7 +349,7 @@ struct kepler_channel_gpfifo_a_v0 { #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR 0x01 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_VP 0x02 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_PPP 0x04 -#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_BSP 0x08 +#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSVLD 0x08 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0 0x10 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE1 0x20 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_ENC 0x40 diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h index 82625c5d68d7..7205d07f5cc9 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h @@ -59,6 +59,7 @@ enum nv_subdev_type { NVDEV_ENGINE_VENC, NVDEV_ENGINE_DISP, NVDEV_ENGINE_PERFMON, + NVDEV_ENGINE_MSVLD, NVDEV_SUBDEV_NR, }; diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/bsp.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/bsp.h index 67662e2c4547..5ce3b620e6a9 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/bsp.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/bsp.h @@ -1,9 +1,4 @@ #ifndef __NOUVEAU_BSP_H__ #define __NOUVEAU_BSP_H__ - extern struct nouveau_oclass nv84_bsp_oclass; -extern struct nouveau_oclass nv98_bsp_oclass; -extern struct nouveau_oclass nvc0_bsp_oclass; -extern struct nouveau_oclass nve0_bsp_oclass; - #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h new file mode 100644 index 000000000000..f031bb9de74c --- /dev/null +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h @@ -0,0 +1,6 @@ +#ifndef __NVKM_MSVLD_H__ +#define __NVKM_MSVLD_H__ +extern struct nouveau_oclass nv98_msvld_oclass; +extern struct nouveau_oclass nvc0_msvld_oclass; +extern struct nouveau_oclass nve0_msvld_oclass; +#endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild index ebd30be3a62d..b410eb1e2228 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild @@ -10,6 +10,7 @@ include $(src)/nvkm/engine/dmaobj/Kbuild include $(src)/nvkm/engine/fifo/Kbuild include $(src)/nvkm/engine/graph/Kbuild include $(src)/nvkm/engine/mpeg/Kbuild +include $(src)/nvkm/engine/msvld/Kbuild include $(src)/nvkm/engine/perfmon/Kbuild include $(src)/nvkm/engine/ppp/Kbuild include $(src)/nvkm/engine/software/Kbuild diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/bsp/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/bsp/Kbuild index da54c5610a67..3c8757202931 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/bsp/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/bsp/Kbuild @@ -1,4 +1 @@ nvkm-y += nvkm/engine/bsp/nv84.o -nvkm-y += nvkm/engine/bsp/nv98.o -nvkm-y += nvkm/engine/bsp/nvc0.o -nvkm-y += nvkm/engine/bsp/nve0.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index eb9f387d7356..7945bba5e794 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -241,6 +241,7 @@ static const u64 disable_map[] = { [NVDEV_ENGINE_VIC] = NV_DEVICE_V0_DISABLE_VIC, [NVDEV_ENGINE_VENC] = NV_DEVICE_V0_DISABLE_VENC, [NVDEV_ENGINE_DISP] = NV_DEVICE_V0_DISABLE_DISP, + [NVDEV_ENGINE_MSVLD] = NV_DEVICE_V0_DISABLE_MSVLD, [NVDEV_SUBDEV_NR] = 0, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c index 130d225377ee..391369a1c034 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c @@ -50,6 +50,7 @@ #include #include #include +#include #include #include #include @@ -93,7 +94,7 @@ gm100_identify(struct nouveau_device *device) #endif device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; #if 0 - device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; #endif @@ -136,7 +137,7 @@ gm100_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_COPY0 ] = &gm204_copy0_oclass; device->oclass[NVDEV_ENGINE_COPY1 ] = &gm204_copy1_oclass; device->oclass[NVDEV_ENGINE_COPY2 ] = &gm204_copy2_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c index f9afee4f844d..90f0e23f582e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c @@ -49,6 +49,7 @@ #include #include #include +#include #include #include #include @@ -253,7 +254,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; @@ -311,7 +312,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; @@ -340,7 +341,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass; @@ -370,7 +371,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; @@ -400,7 +401,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; @@ -430,7 +431,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; @@ -460,7 +461,7 @@ nv50_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass; device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c index 0db51092732a..0e1be5e2472e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c @@ -49,6 +49,7 @@ #include #include #include +#include #include #include #include @@ -84,7 +85,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; device->oclass[NVDEV_ENGINE_GR ] = nvc0_graph_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass; @@ -117,7 +118,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass; @@ -150,7 +151,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; @@ -182,7 +183,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass; @@ -215,7 +216,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; @@ -247,7 +248,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; device->oclass[NVDEV_ENGINE_GR ] = nvc1_graph_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass; @@ -279,7 +280,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; device->oclass[NVDEV_ENGINE_GR ] = nvc8_graph_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass; @@ -312,7 +313,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; device->oclass[NVDEV_ENGINE_GR ] = nvd9_graph_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nvd0_disp_oclass; @@ -342,7 +343,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass; device->oclass[NVDEV_ENGINE_GR ] = nvd7_graph_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass; device->oclass[NVDEV_ENGINE_DISP ] = nvd0_disp_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c index a565bc8b6636..1460a1650d0e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c @@ -50,6 +50,7 @@ #include #include #include +#include #include #include #include @@ -87,7 +88,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass; @@ -121,7 +122,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass; @@ -155,7 +156,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass; @@ -211,7 +212,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = &nvf0_perfmon_oclass; @@ -245,7 +246,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; device->oclass[NVDEV_ENGINE_PERFMON] = &nvf0_perfmon_oclass; @@ -279,7 +280,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; break; @@ -312,7 +313,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass; device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass; device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass; - device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass; + device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass; device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass; device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass; break; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c index b18386b8a842..7183bf1d7f5b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c @@ -60,7 +60,8 @@ nv84_fifo_context_attach(struct nouveau_object *parent, case NVDEV_ENGINE_VP : addr = 0x0040; break; case NVDEV_ENGINE_PPP : case NVDEV_ENGINE_MPEG : addr = 0x0060; break; - case NVDEV_ENGINE_BSP : addr = 0x0080; break; + case NVDEV_ENGINE_BSP : + case NVDEV_ENGINE_MSVLD: addr = 0x0080; break; case NVDEV_ENGINE_CRYPT: addr = 0x00a0; break; case NVDEV_ENGINE_COPY0: addr = 0x00c0; break; default: @@ -96,7 +97,8 @@ nv84_fifo_context_detach(struct nouveau_object *parent, bool suspend, case NVDEV_ENGINE_VP : engn = 3; addr = 0x0040; break; case NVDEV_ENGINE_PPP : case NVDEV_ENGINE_MPEG : engn = 1; addr = 0x0060; break; - case NVDEV_ENGINE_BSP : engn = 5; addr = 0x0080; break; + case NVDEV_ENGINE_BSP : + case NVDEV_ENGINE_MSVLD: engn = 5; addr = 0x0080; break; case NVDEV_ENGINE_CRYPT: engn = 4; addr = 0x00a0; break; case NVDEV_ENGINE_COPY0: engn = 2; addr = 0x00c0; break; default: @@ -147,7 +149,8 @@ nv84_fifo_object_attach(struct nouveau_object *parent, case NVDEV_ENGINE_VP : context |= 0x00400000; break; case NVDEV_ENGINE_CRYPT : case NVDEV_ENGINE_VIC : context |= 0x00500000; break; - case NVDEV_ENGINE_BSP : context |= 0x00600000; break; + case NVDEV_ENGINE_BSP : + case NVDEV_ENGINE_MSVLD : context |= 0x00600000; break; default: return -EINVAL; } @@ -187,6 +190,7 @@ nv84_fifo_chan_ctor_dma(struct nouveau_object *parent, (1ULL << NVDEV_ENGINE_VP) | (1ULL << NVDEV_ENGINE_CRYPT) | (1ULL << NVDEV_ENGINE_BSP) | + (1ULL << NVDEV_ENGINE_MSVLD) | (1ULL << NVDEV_ENGINE_PPP) | (1ULL << NVDEV_ENGINE_COPY0) | (1ULL << NVDEV_ENGINE_VIC), &chan); @@ -260,6 +264,7 @@ nv84_fifo_chan_ctor_ind(struct nouveau_object *parent, (1ULL << NVDEV_ENGINE_VP) | (1ULL << NVDEV_ENGINE_CRYPT) | (1ULL << NVDEV_ENGINE_BSP) | + (1ULL << NVDEV_ENGINE_MSVLD) | (1ULL << NVDEV_ENGINE_PPP) | (1ULL << NVDEV_ENGINE_COPY0) | (1ULL << NVDEV_ENGINE_VIC), &chan); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c index e5d1e969945e..2af40b208860 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c @@ -124,7 +124,7 @@ nvc0_fifo_context_attach(struct nouveau_object *parent, case NVDEV_ENGINE_GR : addr = 0x0210; break; case NVDEV_ENGINE_COPY0: addr = 0x0230; break; case NVDEV_ENGINE_COPY1: addr = 0x0240; break; - case NVDEV_ENGINE_BSP : addr = 0x0270; break; + case NVDEV_ENGINE_MSVLD: addr = 0x0270; break; case NVDEV_ENGINE_VP : addr = 0x0250; break; case NVDEV_ENGINE_PPP : addr = 0x0260; break; default: @@ -161,7 +161,7 @@ nvc0_fifo_context_detach(struct nouveau_object *parent, bool suspend, case NVDEV_ENGINE_GR : addr = 0x0210; break; case NVDEV_ENGINE_COPY0: addr = 0x0230; break; case NVDEV_ENGINE_COPY1: addr = 0x0240; break; - case NVDEV_ENGINE_BSP : addr = 0x0270; break; + case NVDEV_ENGINE_MSVLD: addr = 0x0270; break; case NVDEV_ENGINE_VP : addr = 0x0250; break; case NVDEV_ENGINE_PPP : addr = 0x0260; break; default: @@ -214,7 +214,7 @@ nvc0_fifo_chan_ctor(struct nouveau_object *parent, (1ULL << NVDEV_ENGINE_GR) | (1ULL << NVDEV_ENGINE_COPY0) | (1ULL << NVDEV_ENGINE_COPY1) | - (1ULL << NVDEV_ENGINE_BSP) | + (1ULL << NVDEV_ENGINE_MSVLD) | (1ULL << NVDEV_ENGINE_VP) | (1ULL << NVDEV_ENGINE_PPP), &chan); *pobject = nv_object(chan); @@ -382,7 +382,7 @@ nvc0_fifo_engidx(struct nvc0_fifo_priv *priv, u32 engn) { switch (engn) { case NVDEV_ENGINE_GR : engn = 0; break; - case NVDEV_ENGINE_BSP : engn = 1; break; + case NVDEV_ENGINE_MSVLD: engn = 1; break; case NVDEV_ENGINE_PPP : engn = 2; break; case NVDEV_ENGINE_VP : engn = 3; break; case NVDEV_ENGINE_COPY0: engn = 4; break; @@ -399,7 +399,7 @@ nvc0_fifo_engine(struct nvc0_fifo_priv *priv, u32 engn) { switch (engn) { case 0: engn = NVDEV_ENGINE_GR; break; - case 1: engn = NVDEV_ENGINE_BSP; break; + case 1: engn = NVDEV_ENGINE_MSVLD; break; case 2: engn = NVDEV_ENGINE_PPP; break; case 3: engn = NVDEV_ENGINE_VP; break; case 4: engn = NVDEV_ENGINE_COPY0; break; @@ -548,7 +548,7 @@ nvc0_fifo_fault_engine[] = { { 0x04, "BAR1", NULL, NVDEV_SUBDEV_BAR }, { 0x05, "BAR3", NULL, NVDEV_SUBDEV_INSTMEM }, { 0x07, "PFIFO", NULL, NVDEV_ENGINE_FIFO }, - { 0x10, "PBSP", NULL, NVDEV_ENGINE_BSP }, + { 0x10, "PMSVLD", NULL, NVDEV_ENGINE_MSVLD }, { 0x11, "PPPP", NULL, NVDEV_ENGINE_PPP }, { 0x13, "PCOUNTER" }, { 0x14, "PVP", NULL, NVDEV_ENGINE_VP }, @@ -583,7 +583,7 @@ nvc0_fifo_fault_hubclient[] = { { 0x08, "BAR_WRITE" }, { 0x0b, "PVP" }, { 0x0c, "PPPP" }, - { 0x0d, "PBSP" }, + { 0x0d, "PMSVLD" }, { 0x11, "PCOUNTER" }, { 0x12, "PDAEMON" }, { 0x14, "CCACHE" }, @@ -941,7 +941,7 @@ nvc0_fifo_init(struct nouveau_object *object) nv_wr32(priv, 0x002208, ~(1 << 0)); /* PGRAPH */ nv_wr32(priv, 0x00220c, ~(1 << 1)); /* PVP */ nv_wr32(priv, 0x002210, ~(1 << 1)); /* PPP */ - nv_wr32(priv, 0x002214, ~(1 << 1)); /* PBSP */ + nv_wr32(priv, 0x002214, ~(1 << 1)); /* PMSVLD */ nv_wr32(priv, 0x002218, ~(1 << 2)); /* PCE0 */ nv_wr32(priv, 0x00221c, ~(1 << 1)); /* PCE1 */ } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c index bf2b9e2df3d0..b415b309f4b8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c @@ -50,7 +50,7 @@ static const struct { (1ULL << NVDEV_ENGINE_COPY2)), _(NVDEV_ENGINE_VP , 0), _(NVDEV_ENGINE_PPP , 0), - _(NVDEV_ENGINE_BSP , 0), + _(NVDEV_ENGINE_MSVLD , 0), _(NVDEV_ENGINE_COPY0 , 0), _(NVDEV_ENGINE_COPY1 , 0), _(NVDEV_ENGINE_VENC , 0), @@ -149,7 +149,7 @@ nve0_fifo_context_attach(struct nouveau_object *parent, nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; return 0; case NVDEV_ENGINE_GR : addr = 0x0210; break; - case NVDEV_ENGINE_BSP : addr = 0x0270; break; + case NVDEV_ENGINE_MSVLD: addr = 0x0270; break; case NVDEV_ENGINE_VP : addr = 0x0250; break; case NVDEV_ENGINE_PPP : addr = 0x0260; break; default: @@ -187,7 +187,7 @@ nve0_fifo_context_detach(struct nouveau_object *parent, bool suspend, case NVDEV_ENGINE_COPY1: case NVDEV_ENGINE_COPY2: addr = 0x0000; break; case NVDEV_ENGINE_GR : addr = 0x0210; break; - case NVDEV_ENGINE_BSP : addr = 0x0270; break; + case NVDEV_ENGINE_MSVLD: addr = 0x0270; break; case NVDEV_ENGINE_VP : addr = 0x0250; break; case NVDEV_ENGINE_PPP : addr = 0x0260; break; default: @@ -416,7 +416,7 @@ nve0_fifo_engidx(struct nve0_fifo_priv *priv, u32 engn) switch (engn) { case NVDEV_ENGINE_GR : case NVDEV_ENGINE_COPY2: engn = 0; break; - case NVDEV_ENGINE_BSP : engn = 1; break; + case NVDEV_ENGINE_MSVLD: engn = 1; break; case NVDEV_ENGINE_PPP : engn = 2; break; case NVDEV_ENGINE_VP : engn = 3; break; case NVDEV_ENGINE_COPY0: engn = 4; break; @@ -619,7 +619,7 @@ nve0_fifo_fault_engine[] = { { 0x07, "PBDMA0", NULL, NVDEV_ENGINE_FIFO }, { 0x08, "PBDMA1", NULL, NVDEV_ENGINE_FIFO }, { 0x09, "PBDMA2", NULL, NVDEV_ENGINE_FIFO }, - { 0x10, "MSVLD", NULL, NVDEV_ENGINE_BSP }, + { 0x10, "MSVLD", NULL, NVDEV_ENGINE_MSVLD }, { 0x11, "MSPPP", NULL, NVDEV_ENGINE_PPP }, { 0x13, "PERF" }, { 0x14, "MSPDEC", NULL, NVDEV_ENGINE_VP }, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msvld/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/Kbuild new file mode 100644 index 000000000000..1deb463a2b0b --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/Kbuild @@ -0,0 +1,3 @@ +nvkm-y += nvkm/engine/msvld/nv98.o +nvkm-y += nvkm/engine/msvld/nvc0.o +nvkm-y += nvkm/engine/msvld/nve0.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/bsp/nv98.c b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/nv98.c similarity index 81% rename from drivers/gpu/drm/nouveau/nvkm/engine/bsp/nv98.c rename to drivers/gpu/drm/nouveau/nvkm/engine/msvld/nv98.c index 6b089e022fd2..4bafba59226c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/bsp/nv98.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/nv98.c @@ -23,18 +23,18 @@ */ #include -#include +#include -struct nv98_bsp_priv { +struct nv98_msvld_priv { struct nouveau_falcon base; }; /******************************************************************************* - * BSP object classes + * MSVLD object classes ******************************************************************************/ static struct nouveau_oclass -nv98_bsp_sclass[] = { +nv98_msvld_sclass[] = { { 0x88b1, &nouveau_object_ofuncs }, { 0x85b1, &nouveau_object_ofuncs }, { 0x86b1, &nouveau_object_ofuncs }, @@ -42,12 +42,12 @@ nv98_bsp_sclass[] = { }; /******************************************************************************* - * PBSP context + * PMSVLD context ******************************************************************************/ static struct nouveau_oclass -nv98_bsp_cclass = { - .handle = NV_ENGCTX(BSP, 0x98), +nv98_msvld_cclass = { + .handle = NV_ENGCTX(MSVLD, 0x98), .ofuncs = &(struct nouveau_ofuncs) { .ctor = _nouveau_falcon_context_ctor, .dtor = _nouveau_falcon_context_dtor, @@ -59,13 +59,13 @@ nv98_bsp_cclass = { }; /******************************************************************************* - * PBSP engine/subdev functions + * PMSVLD engine/subdev functions ******************************************************************************/ static int -nv98_bsp_init(struct nouveau_object *object) +nv98_msvld_init(struct nouveau_object *object) { - struct nv98_bsp_priv *priv = (void *)object; + struct nv98_msvld_priv *priv = (void *)object; int ret; ret = nouveau_falcon_init(&priv->base); @@ -78,32 +78,32 @@ nv98_bsp_init(struct nouveau_object *object) } static int -nv98_bsp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +nv98_msvld_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_object **pobject) { - struct nv98_bsp_priv *priv; + struct nv98_msvld_priv *priv; int ret; ret = nouveau_falcon_create(parent, engine, oclass, 0x084000, true, - "PBSP", "bsp", &priv); + "PMSVLD", "msvld", &priv); *pobject = nv_object(priv); if (ret) return ret; nv_subdev(priv)->unit = 0x04008000; - nv_engine(priv)->cclass = &nv98_bsp_cclass; - nv_engine(priv)->sclass = nv98_bsp_sclass; + nv_engine(priv)->cclass = &nv98_msvld_cclass; + nv_engine(priv)->sclass = nv98_msvld_sclass; return 0; } struct nouveau_oclass -nv98_bsp_oclass = { - .handle = NV_ENGINE(BSP, 0x98), +nv98_msvld_oclass = { + .handle = NV_ENGINE(MSVLD, 0x98), .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nv98_bsp_ctor, + .ctor = nv98_msvld_ctor, .dtor = _nouveau_falcon_dtor, - .init = nv98_bsp_init, + .init = nv98_msvld_init, .fini = _nouveau_falcon_fini, .rd32 = _nouveau_falcon_rd32, .wr32 = _nouveau_falcon_wr32, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/bsp/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/nvc0.c similarity index 81% rename from drivers/gpu/drm/nouveau/nvkm/engine/bsp/nvc0.c rename to drivers/gpu/drm/nouveau/nvkm/engine/msvld/nvc0.c index ce860de43e61..fd2ac0d620c6 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/bsp/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/nvc0.c @@ -23,29 +23,29 @@ */ #include -#include +#include -struct nvc0_bsp_priv { +struct nvc0_msvld_priv { struct nouveau_falcon base; }; /******************************************************************************* - * BSP object classes + * MSVLD object classes ******************************************************************************/ static struct nouveau_oclass -nvc0_bsp_sclass[] = { +nvc0_msvld_sclass[] = { { 0x90b1, &nouveau_object_ofuncs }, {}, }; /******************************************************************************* - * PBSP context + * PMSVLD context ******************************************************************************/ static struct nouveau_oclass -nvc0_bsp_cclass = { - .handle = NV_ENGCTX(BSP, 0xc0), +nvc0_msvld_cclass = { + .handle = NV_ENGCTX(MSVLD, 0xc0), .ofuncs = &(struct nouveau_ofuncs) { .ctor = _nouveau_falcon_context_ctor, .dtor = _nouveau_falcon_context_dtor, @@ -57,13 +57,13 @@ nvc0_bsp_cclass = { }; /******************************************************************************* - * PBSP engine/subdev functions + * PMSVLD engine/subdev functions ******************************************************************************/ static int -nvc0_bsp_init(struct nouveau_object *object) +nvc0_msvld_init(struct nouveau_object *object) { - struct nvc0_bsp_priv *priv = (void *)object; + struct nvc0_msvld_priv *priv = (void *)object; int ret; ret = nouveau_falcon_init(&priv->base); @@ -76,33 +76,33 @@ nvc0_bsp_init(struct nouveau_object *object) } static int -nvc0_bsp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +nvc0_msvld_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_object **pobject) { - struct nvc0_bsp_priv *priv; + struct nvc0_msvld_priv *priv; int ret; ret = nouveau_falcon_create(parent, engine, oclass, 0x084000, true, - "PBSP", "bsp", &priv); + "PMSVLD", "msvld", &priv); *pobject = nv_object(priv); if (ret) return ret; nv_subdev(priv)->unit = 0x00008000; nv_subdev(priv)->intr = nouveau_falcon_intr; - nv_engine(priv)->cclass = &nvc0_bsp_cclass; - nv_engine(priv)->sclass = nvc0_bsp_sclass; + nv_engine(priv)->cclass = &nvc0_msvld_cclass; + nv_engine(priv)->sclass = nvc0_msvld_sclass; return 0; } struct nouveau_oclass -nvc0_bsp_oclass = { - .handle = NV_ENGINE(BSP, 0xc0), +nvc0_msvld_oclass = { + .handle = NV_ENGINE(MSVLD, 0xc0), .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_bsp_ctor, + .ctor = nvc0_msvld_ctor, .dtor = _nouveau_falcon_dtor, - .init = nvc0_bsp_init, + .init = nvc0_msvld_init, .fini = _nouveau_falcon_fini, .rd32 = _nouveau_falcon_rd32, .wr32 = _nouveau_falcon_wr32, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/bsp/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/nve0.c similarity index 81% rename from drivers/gpu/drm/nouveau/nvkm/engine/bsp/nve0.c rename to drivers/gpu/drm/nouveau/nvkm/engine/msvld/nve0.c index ba6aeca0285e..4b3d3ca80eff 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/bsp/nve0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/msvld/nve0.c @@ -23,29 +23,29 @@ */ #include -#include +#include -struct nve0_bsp_priv { +struct nve0_msvld_priv { struct nouveau_falcon base; }; /******************************************************************************* - * BSP object classes + * MSVLD object classes ******************************************************************************/ static struct nouveau_oclass -nve0_bsp_sclass[] = { +nve0_msvld_sclass[] = { { 0x95b1, &nouveau_object_ofuncs }, {}, }; /******************************************************************************* - * PBSP context + * PMSVLD context ******************************************************************************/ static struct nouveau_oclass -nve0_bsp_cclass = { - .handle = NV_ENGCTX(BSP, 0xe0), +nve0_msvld_cclass = { + .handle = NV_ENGCTX(MSVLD, 0xe0), .ofuncs = &(struct nouveau_ofuncs) { .ctor = _nouveau_falcon_context_ctor, .dtor = _nouveau_falcon_context_dtor, @@ -57,13 +57,13 @@ nve0_bsp_cclass = { }; /******************************************************************************* - * PBSP engine/subdev functions + * PMSVLD engine/subdev functions ******************************************************************************/ static int -nve0_bsp_init(struct nouveau_object *object) +nve0_msvld_init(struct nouveau_object *object) { - struct nve0_bsp_priv *priv = (void *)object; + struct nve0_msvld_priv *priv = (void *)object; int ret; ret = nouveau_falcon_init(&priv->base); @@ -76,33 +76,33 @@ nve0_bsp_init(struct nouveau_object *object) } static int -nve0_bsp_ctor(struct nouveau_object *parent, struct nouveau_object *engine, +nve0_msvld_ctor(struct nouveau_object *parent, struct nouveau_object *engine, struct nouveau_oclass *oclass, void *data, u32 size, struct nouveau_object **pobject) { - struct nve0_bsp_priv *priv; + struct nve0_msvld_priv *priv; int ret; ret = nouveau_falcon_create(parent, engine, oclass, 0x084000, true, - "PBSP", "bsp", &priv); + "PMSVLD", "msvld", &priv); *pobject = nv_object(priv); if (ret) return ret; nv_subdev(priv)->unit = 0x00008000; nv_subdev(priv)->intr = nouveau_falcon_intr; - nv_engine(priv)->cclass = &nve0_bsp_cclass; - nv_engine(priv)->sclass = nve0_bsp_sclass; + nv_engine(priv)->cclass = &nve0_msvld_cclass; + nv_engine(priv)->sclass = nve0_msvld_sclass; return 0; } struct nouveau_oclass -nve0_bsp_oclass = { - .handle = NV_ENGINE(BSP, 0xe0), +nve0_msvld_oclass = { + .handle = NV_ENGINE(MSVLD, 0xe0), .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nve0_bsp_ctor, + .ctor = nve0_msvld_ctor, .dtor = _nouveau_falcon_dtor, - .init = nve0_bsp_init, + .init = nve0_msvld_init, .fini = _nouveau_falcon_fini, .rd32 = _nouveau_falcon_rd32, .wr32 = _nouveau_falcon_wr32, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv98.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv98.c index a773253a17f6..820f069fbaac 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv98.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv98.c @@ -34,14 +34,14 @@ nv98_devinit_disable(struct nouveau_devinit *devinit) if (!(r001540 & 0x40000000)) { disable |= (1ULL << NVDEV_ENGINE_VP); - disable |= (1ULL << NVDEV_ENGINE_BSP); + disable |= (1ULL << NVDEV_ENGINE_MSVLD); disable |= (1ULL << NVDEV_ENGINE_PPP); } if (!(r00154c & 0x00000004)) disable |= (1ULL << NVDEV_ENGINE_DISP); if (!(r00154c & 0x00000020)) - disable |= (1ULL << NVDEV_ENGINE_BSP); + disable |= (1ULL << NVDEV_ENGINE_MSVLD); if (!(r00154c & 0x00000040)) disable |= (1ULL << NVDEV_ENGINE_CRYPT); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nva3.c index b9cd9e53f760..f662a261cc65 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nva3.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nva3.c @@ -74,7 +74,7 @@ nva3_devinit_disable(struct nouveau_devinit *devinit) if (!(r00154c & 0x00000004)) disable |= (1ULL << NVDEV_ENGINE_DISP); if (!(r00154c & 0x00000020)) - disable |= (1ULL << NVDEV_ENGINE_BSP); + disable |= (1ULL << NVDEV_ENGINE_MSVLD); if (!(r00154c & 0x00000200)) disable |= (1ULL << NVDEV_ENGINE_COPY0); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvaf.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvaf.c index 3729846a8e5c..6f8ef894e4ef 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvaf.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvaf.c @@ -40,7 +40,7 @@ nvaf_devinit_disable(struct nouveau_devinit *devinit) if (!(r00154c & 0x00000004)) disable |= (1ULL << NVDEV_ENGINE_DISP); if (!(r00154c & 0x00000020)) - disable |= (1ULL << NVDEV_ENGINE_BSP); + disable |= (1ULL << NVDEV_ENGINE_MSVLD); if (!(r00154c & 0x00000040)) disable |= (1ULL << NVDEV_ENGINE_VIC); if (!(r00154c & 0x00000200)) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvc0.c index 80bd7f5eda3d..ac699a366f60 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvc0.c @@ -75,7 +75,7 @@ nvc0_devinit_disable(struct nouveau_devinit *devinit) } if (r022500 & 0x00000004) - disable |= (1ULL << NVDEV_ENGINE_BSP); + disable |= (1ULL << NVDEV_ENGINE_MSVLD); if (r022500 & 0x00000008) disable |= (1ULL << NVDEV_ENGINE_VENC); if (r022500 & 0x00000100) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c index 4150b0d10af8..df07c046213e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c @@ -189,6 +189,9 @@ nv50_fb_intr(struct nouveau_subdev *subdev) const struct nouveau_enum *orig_en = en; while (en->name && en->value == st0 && en->data2) { engine = nouveau_engine(subdev, en->data2); + /*XXX: clean this up */ + if (!engine && en->data2 == NVDEV_ENGINE_BSP) + engine = nouveau_engine(subdev, NVDEV_ENGINE_MSVLD); if (engine) { engctx = nouveau_engctx_get(engine, chan); if (engctx) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c index aa1c690fe0e1..bb1346f6fa12 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c @@ -31,7 +31,7 @@ nv98_mc_intr[] = { { 0x00000100, NVDEV_ENGINE_FIFO }, { 0x00001000, NVDEV_ENGINE_GR }, { 0x00004000, NVDEV_ENGINE_CRYPT }, /* NV84:NVA3 */ - { 0x00008000, NVDEV_ENGINE_BSP }, + { 0x00008000, NVDEV_ENGINE_MSVLD }, { 0x00020000, NVDEV_ENGINE_VP }, { 0x00040000, NVDEV_SUBDEV_PMU }, /* NVA3:NVC0 */ { 0x00080000, NVDEV_SUBDEV_THERM }, /* NVA3:NVC0 */ diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c index 7053ae3db08e..1e352152cadd 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c @@ -34,7 +34,7 @@ nvc0_mc_intr[] = { { 0x00000100, NVDEV_ENGINE_FIFO }, { 0x00001000, NVDEV_ENGINE_GR }, { 0x00002000, NVDEV_SUBDEV_FB }, - { 0x00008000, NVDEV_ENGINE_BSP }, + { 0x00008000, NVDEV_ENGINE_MSVLD }, { 0x00040000, NVDEV_SUBDEV_THERM }, { 0x00020000, NVDEV_ENGINE_VP }, { 0x00100000, NVDEV_SUBDEV_TIMER }, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c index 6ddc65dc684d..eabf2bab1d10 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c @@ -176,7 +176,8 @@ nv50_vm_flush(struct nouveau_vm *vm) case NVDEV_SUBDEV_BAR : vme = 0x06; break; case NVDEV_ENGINE_PPP : case NVDEV_ENGINE_MPEG : vme = 0x08; break; - case NVDEV_ENGINE_BSP : vme = 0x09; break; + case NVDEV_ENGINE_BSP : + case NVDEV_ENGINE_MSVLD: vme = 0x09; break; case NVDEV_ENGINE_CRYPT: vme = 0x0a; break; case NVDEV_ENGINE_COPY0: vme = 0x0d; break; default: -- 2.39.5