From ee2d16d7b3c95a65ed0434841568bd3f82712338 Mon Sep 17 00:00:00 2001 From: "Lad, Prabhakar" Date: Tue, 21 Jan 2014 02:20:57 -0300 Subject: [PATCH] [media] mt9p031: Check return value of clk_prepare_enable/clk_set_rate clk_set_rate(), clk_prepare_enable() functions can fail, so check the return values to avoid surprises. Signed-off-by: Lad, Prabhakar Signed-off-by: Laurent Pinchart Signed-off-by: Mauro Carvalho Chehab --- drivers/media/i2c/mt9p031.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/media/i2c/mt9p031.c b/drivers/media/i2c/mt9p031.c index fec76d3f056c..dd7b258a9802 100644 --- a/drivers/media/i2c/mt9p031.c +++ b/drivers/media/i2c/mt9p031.c @@ -232,12 +232,15 @@ static int mt9p031_clk_setup(struct mt9p031 *mt9p031) struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); struct mt9p031_platform_data *pdata = mt9p031->pdata; + int ret; mt9p031->clk = devm_clk_get(&client->dev, NULL); if (IS_ERR(mt9p031->clk)) return PTR_ERR(mt9p031->clk); - clk_set_rate(mt9p031->clk, pdata->ext_freq); + ret = clk_set_rate(mt9p031->clk, pdata->ext_freq); + if (ret < 0) + return ret; /* If the external clock frequency is out of bounds for the PLL use the * pixel clock divider only and disable the PLL. @@ -318,8 +321,14 @@ static int mt9p031_power_on(struct mt9p031 *mt9p031) return ret; /* Enable clock */ - if (mt9p031->clk) - clk_prepare_enable(mt9p031->clk); + if (mt9p031->clk) { + ret = clk_prepare_enable(mt9p031->clk); + if (ret) { + regulator_bulk_disable(ARRAY_SIZE(mt9p031->regulators), + mt9p031->regulators); + return ret; + } + } /* Now RESET_BAR must be high */ if (gpio_is_valid(mt9p031->reset)) { -- 2.39.5