From ef2a27059226327228238a55208d8c11b80013c9 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 30 Dec 2015 21:05:09 +0100 Subject: [PATCH] ARM: realview: set up cache correctly on the PB11MPCore The L2 cache comes up in a "safe mode" on the PB11MPCore, as it has several issues. This sets it up properly with the right size and associativity, also requiring the outer sync to be disabled for the machine to boot properly. Cc: Russell King Cc: Arnd Bergmann Signed-off-by: Linus Walleij Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/arm-realview-pb11mp.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/arm-realview-pb11mp.dts b/arch/arm/boot/dts/arm-realview-pb11mp.dts index 896bd21d320c..da755c9851a7 100644 --- a/arch/arm/boot/dts/arm-realview-pb11mp.dts +++ b/arch/arm/boot/dts/arm-realview-pb11mp.dts @@ -99,6 +99,19 @@ <0 31 IRQ_TYPE_LEVEL_HIGH>; cache-unified; cache-level = <2>; + /* + * Override default cache size, sets and + * associativity as these may be erroneously set + * up by boot loader(s), probably for safety + * since th outer sync operation can cause the + * cache to hang unless disabled. + */ + cache-size = <1048576>; // 1MB + cache-sets = <4096>; + cache-line-size = <32>; + arm,shared-override; + arm,parity-enable; + arm,outer-sync-disable; }; scu@1f000000 { -- 2.39.2