From fd166a1832db138f22ad95eacd0879af30742f57 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 20 Aug 2015 14:54:07 +1000 Subject: [PATCH] drm/nouveau/disp: cosmetic changes This is purely preparation for upcoming commits, there should be no code changes here. Signed-off-by: Ben Skeggs --- .../drm/nouveau/include/nvkm/engine/disp.h | 2 +- .../gpu/drm/nouveau/nvkm/engine/disp/base.c | 6 +- .../drm/nouveau/nvkm/engine/disp/dacnv50.c | 20 +- .../gpu/drm/nouveau/nvkm/engine/disp/dport.c | 8 +- .../gpu/drm/nouveau/nvkm/engine/disp/g84.c | 36 +- .../gpu/drm/nouveau/nvkm/engine/disp/g94.c | 36 +- .../gpu/drm/nouveau/nvkm/engine/disp/gf110.c | 416 +++++++------- .../gpu/drm/nouveau/nvkm/engine/disp/gk104.c | 34 +- .../gpu/drm/nouveau/nvkm/engine/disp/gk110.c | 34 +- .../gpu/drm/nouveau/nvkm/engine/disp/gm107.c | 34 +- .../gpu/drm/nouveau/nvkm/engine/disp/gm204.c | 36 +- .../gpu/drm/nouveau/nvkm/engine/disp/gt200.c | 36 +- .../gpu/drm/nouveau/nvkm/engine/disp/gt215.c | 38 +- .../drm/nouveau/nvkm/engine/disp/hdagf110.c | 18 +- .../drm/nouveau/nvkm/engine/disp/hdagt215.c | 16 +- .../drm/nouveau/nvkm/engine/disp/hdmig84.c | 44 +- .../drm/nouveau/nvkm/engine/disp/hdmigf110.c | 28 +- .../drm/nouveau/nvkm/engine/disp/hdmigk104.c | 30 +- .../drm/nouveau/nvkm/engine/disp/hdmigt215.c | 44 +- .../gpu/drm/nouveau/nvkm/engine/disp/nv04.c | 54 +- .../gpu/drm/nouveau/nvkm/engine/disp/nv50.c | 535 +++++++++--------- .../gpu/drm/nouveau/nvkm/engine/disp/nv50.h | 10 +- .../drm/nouveau/nvkm/engine/disp/piornv50.c | 8 +- .../gpu/drm/nouveau/nvkm/engine/disp/sorg94.c | 44 +- .../drm/nouveau/nvkm/engine/disp/sorgf110.c | 32 +- .../drm/nouveau/nvkm/engine/disp/sorgm204.c | 46 +- .../drm/nouveau/nvkm/engine/disp/sornv50.c | 8 +- drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c | 6 +- 28 files changed, 826 insertions(+), 833 deletions(-) diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h index a5e1ed81312f..24bce1a93dbf 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h @@ -4,7 +4,7 @@ #include struct nvkm_disp { - struct nvkm_engine base; + struct nvkm_engine engine; struct list_head outp; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c index 23d1b5c0dc16..2090e90d6770 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c @@ -127,7 +127,7 @@ _nvkm_disp_fini(struct nvkm_object *object, bool suspend) goto fail_outp; } - return nvkm_engine_fini(&disp->base, suspend); + return nvkm_engine_fini(&disp->engine, suspend); fail_outp: list_for_each_entry_continue_reverse(outp, &disp->outp, head) { @@ -144,7 +144,7 @@ _nvkm_disp_init(struct nvkm_object *object) struct nvkm_output *outp; int ret; - ret = nvkm_engine_init(&disp->base); + ret = nvkm_engine_init(&disp->engine); if (ret) return ret; @@ -179,7 +179,7 @@ _nvkm_disp_dtor(struct nvkm_object *object) } } - nvkm_engine_destroy(&disp->base); + nvkm_engine_destroy(&disp->engine); } int diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c index 0f7d1ec4d37e..f64dec917f85 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c @@ -53,9 +53,9 @@ nv50_dac_power(NV50_DISP_MTHD_V1) } else return ret; - nv_wait(priv, 0x61a004 + doff, 0x80000000, 0x00000000); - nv_mask(priv, 0x61a004 + doff, 0xc000007f, 0x80000000 | stat); - nv_wait(priv, 0x61a004 + doff, 0x80000000, 0x00000000); + nv_wait(disp, 0x61a004 + doff, 0x80000000, 0x00000000); + nv_mask(disp, 0x61a004 + doff, 0xc000007f, 0x80000000 | stat); + nv_wait(disp, 0x61a004 + doff, 0x80000000, 0x00000000); return 0; } @@ -79,18 +79,18 @@ nv50_dac_sense(NV50_DISP_MTHD_V1) } else return ret; - nv_mask(priv, 0x61a004 + doff, 0x807f0000, 0x80150000); - nv_wait(priv, 0x61a004 + doff, 0x80000000, 0x00000000); + nv_mask(disp, 0x61a004 + doff, 0x807f0000, 0x80150000); + nv_wait(disp, 0x61a004 + doff, 0x80000000, 0x00000000); - nv_wr32(priv, 0x61a00c + doff, 0x00100000 | loadval); + nv_wr32(disp, 0x61a00c + doff, 0x00100000 | loadval); mdelay(9); udelay(500); - loadval = nv_mask(priv, 0x61a00c + doff, 0xffffffff, 0x00000000); + loadval = nv_mask(disp, 0x61a00c + doff, 0xffffffff, 0x00000000); - nv_mask(priv, 0x61a004 + doff, 0x807f0000, 0x80550000); - nv_wait(priv, 0x61a004 + doff, 0x80000000, 0x00000000); + nv_mask(disp, 0x61a004 + doff, 0x807f0000, 0x80550000); + nv_wait(disp, 0x61a004 + doff, 0x80000000, 0x00000000); - nv_debug(priv, "DAC%d sense: 0x%08x\n", outp->or, loadval); + nv_debug(disp, "DAC%d sense: 0x%08x\n", outp->or, loadval); if (!(loadval & 0x80000000)) return -ETIMEDOUT; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dport.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dport.c index 68347661adca..bc24ae70b405 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/dport.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/dport.c @@ -322,7 +322,7 @@ void nvkm_dp_train(struct work_struct *w) { struct nvkm_output_dp *outp = container_of(w, typeof(*outp), lt.work); - struct nv50_disp_priv *priv = (void *)nvkm_disp(outp); + struct nv50_disp *disp = (void *)nvkm_disp(outp); const struct dp_rates *cfg = nvkm_dp_rates; struct dp_state _dp = { .outp = outp, @@ -330,11 +330,11 @@ nvkm_dp_train(struct work_struct *w) u32 datarate = 0; int ret; - if (!outp->base.info.location && priv->sor.magic) - priv->sor.magic(&outp->base); + if (!outp->base.info.location && disp->sor.magic) + disp->sor.magic(&outp->base); /* bring capabilities within encoder limits */ - if (nv_mclass(priv) < GF110_DISP) + if (nv_mclass(disp) < GF110_DISP) outp->dpcd[2] &= ~DPCD_RC02_TPS3_SUPPORTED; if ((outp->dpcd[2] & 0x1f) > outp->base.info.dpconf.link_nr) { outp->dpcd[2] &= ~DPCD_RC02_MAX_LANE_COUNT; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c index a0dcf534cb20..a0801846b477 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c @@ -223,33 +223,33 @@ g84_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nv50_disp_priv *priv; + struct nv50_disp *disp; int ret; ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP", - "display", &priv); - *pobject = nv_object(priv); + "display", &disp); + *pobject = nv_object(disp); if (ret) return ret; - ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent); + ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &disp->uevent); if (ret) return ret; - nv_engine(priv)->sclass = g84_disp_main_oclass; - nv_engine(priv)->cclass = &nv50_disp_cclass; - nv_subdev(priv)->intr = nv50_disp_intr; - INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor); - priv->sclass = g84_disp_sclass; - priv->head.nr = 2; - priv->dac.nr = 3; - priv->sor.nr = 2; - priv->pior.nr = 3; - priv->dac.power = nv50_dac_power; - priv->dac.sense = nv50_dac_sense; - priv->sor.power = nv50_sor_power; - priv->sor.hdmi = g84_hdmi_ctrl; - priv->pior.power = nv50_pior_power; + nv_engine(disp)->sclass = g84_disp_main_oclass; + nv_engine(disp)->cclass = &nv50_disp_cclass; + nv_subdev(disp)->intr = nv50_disp_intr; + INIT_WORK(&disp->supervisor, nv50_disp_intr_supervisor); + disp->sclass = g84_disp_sclass; + disp->head.nr = 2; + disp->dac.nr = 3; + disp->sor.nr = 2; + disp->pior.nr = 3; + disp->dac.power = nv50_dac_power; + disp->dac.sense = nv50_dac_sense; + disp->sor.power = nv50_sor_power; + disp->sor.hdmi = g84_hdmi_ctrl; + disp->pior.power = nv50_pior_power; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c index 1ab0d0ae3cc8..9082fb71cda9 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c @@ -83,33 +83,33 @@ g94_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nv50_disp_priv *priv; + struct nv50_disp *disp; int ret; ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP", - "display", &priv); - *pobject = nv_object(priv); + "display", &disp); + *pobject = nv_object(disp); if (ret) return ret; - ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent); + ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &disp->uevent); if (ret) return ret; - nv_engine(priv)->sclass = g94_disp_main_oclass; - nv_engine(priv)->cclass = &nv50_disp_cclass; - nv_subdev(priv)->intr = nv50_disp_intr; - INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor); - priv->sclass = g94_disp_sclass; - priv->head.nr = 2; - priv->dac.nr = 3; - priv->sor.nr = 4; - priv->pior.nr = 3; - priv->dac.power = nv50_dac_power; - priv->dac.sense = nv50_dac_sense; - priv->sor.power = nv50_sor_power; - priv->sor.hdmi = g84_hdmi_ctrl; - priv->pior.power = nv50_pior_power; + nv_engine(disp)->sclass = g94_disp_main_oclass; + nv_engine(disp)->cclass = &nv50_disp_cclass; + nv_subdev(disp)->intr = nv50_disp_intr; + INIT_WORK(&disp->supervisor, nv50_disp_intr_supervisor); + disp->sclass = g94_disp_sclass; + disp->head.nr = 2; + disp->dac.nr = 3; + disp->sor.nr = 4; + disp->pior.nr = 3; + disp->dac.power = nv50_dac_power; + disp->dac.sense = nv50_dac_sense; + disp->sor.power = nv50_sor_power; + disp->sor.hdmi = g84_hdmi_ctrl; + disp->pior.power = nv50_pior_power; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gf110.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gf110.c index 7f2f05f78cc8..3301fedfe768 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gf110.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gf110.c @@ -46,17 +46,17 @@ static void gf110_disp_chan_uevent_fini(struct nvkm_event *event, int type, int index) { - struct nv50_disp_priv *priv = container_of(event, typeof(*priv), uevent); - nv_mask(priv, 0x610090, 0x00000001 << index, 0x00000000 << index); - nv_wr32(priv, 0x61008c, 0x00000001 << index); + struct nv50_disp *disp = container_of(event, typeof(*disp), uevent); + nv_mask(disp, 0x610090, 0x00000001 << index, 0x00000000 << index); + nv_wr32(disp, 0x61008c, 0x00000001 << index); } static void gf110_disp_chan_uevent_init(struct nvkm_event *event, int types, int index) { - struct nv50_disp_priv *priv = container_of(event, typeof(*priv), uevent); - nv_wr32(priv, 0x61008c, 0x00000001 << index); - nv_mask(priv, 0x610090, 0x00000001 << index, 0x00000001 << index); + struct nv50_disp *disp = container_of(event, typeof(*disp), uevent); + nv_wr32(disp, 0x61008c, 0x00000001 << index); + nv_mask(disp, 0x610090, 0x00000001 << index, 0x00000001 << index); } const struct nvkm_event_func @@ -91,7 +91,7 @@ gf110_disp_dmac_object_detach(struct nvkm_object *parent, int cookie) static int gf110_disp_dmac_init(struct nvkm_object *object) { - struct nv50_disp_priv *priv = (void *)object->engine; + struct nv50_disp *disp = (void *)object->engine; struct nv50_disp_dmac *dmac = (void *)object; int chid = dmac->base.chid; int ret; @@ -101,20 +101,20 @@ gf110_disp_dmac_init(struct nvkm_object *object) return ret; /* enable error reporting */ - nv_mask(priv, 0x6100a0, 0x00000001 << chid, 0x00000001 << chid); + nv_mask(disp, 0x6100a0, 0x00000001 << chid, 0x00000001 << chid); /* initialise channel for dma command submission */ - nv_wr32(priv, 0x610494 + (chid * 0x0010), dmac->push); - nv_wr32(priv, 0x610498 + (chid * 0x0010), 0x00010000); - nv_wr32(priv, 0x61049c + (chid * 0x0010), 0x00000001); - nv_mask(priv, 0x610490 + (chid * 0x0010), 0x00000010, 0x00000010); - nv_wr32(priv, 0x640000 + (chid * 0x1000), 0x00000000); - nv_wr32(priv, 0x610490 + (chid * 0x0010), 0x00000013); + nv_wr32(disp, 0x610494 + (chid * 0x0010), dmac->push); + nv_wr32(disp, 0x610498 + (chid * 0x0010), 0x00010000); + nv_wr32(disp, 0x61049c + (chid * 0x0010), 0x00000001); + nv_mask(disp, 0x610490 + (chid * 0x0010), 0x00000010, 0x00000010); + nv_wr32(disp, 0x640000 + (chid * 0x1000), 0x00000000); + nv_wr32(disp, 0x610490 + (chid * 0x0010), 0x00000013); /* wait for it to go inactive */ - if (!nv_wait(priv, 0x610490 + (chid * 0x10), 0x80000000, 0x00000000)) { + if (!nv_wait(disp, 0x610490 + (chid * 0x10), 0x80000000, 0x00000000)) { nv_error(dmac, "init: 0x%08x\n", - nv_rd32(priv, 0x610490 + (chid * 0x10))); + nv_rd32(disp, 0x610490 + (chid * 0x10))); return -EBUSY; } @@ -124,23 +124,23 @@ gf110_disp_dmac_init(struct nvkm_object *object) static int gf110_disp_dmac_fini(struct nvkm_object *object, bool suspend) { - struct nv50_disp_priv *priv = (void *)object->engine; + struct nv50_disp *disp = (void *)object->engine; struct nv50_disp_dmac *dmac = (void *)object; int chid = dmac->base.chid; /* deactivate channel */ - nv_mask(priv, 0x610490 + (chid * 0x0010), 0x00001010, 0x00001000); - nv_mask(priv, 0x610490 + (chid * 0x0010), 0x00000003, 0x00000000); - if (!nv_wait(priv, 0x610490 + (chid * 0x10), 0x001e0000, 0x00000000)) { + nv_mask(disp, 0x610490 + (chid * 0x0010), 0x00001010, 0x00001000); + nv_mask(disp, 0x610490 + (chid * 0x0010), 0x00000003, 0x00000000); + if (!nv_wait(disp, 0x610490 + (chid * 0x10), 0x001e0000, 0x00000000)) { nv_error(dmac, "fini: 0x%08x\n", - nv_rd32(priv, 0x610490 + (chid * 0x10))); + nv_rd32(disp, 0x610490 + (chid * 0x10))); if (suspend) return -EBUSY; } /* disable error reporting and completion notification */ - nv_mask(priv, 0x610090, 0x00000001 << chid, 0x00000000); - nv_mask(priv, 0x6100a0, 0x00000001 << chid, 0x00000000); + nv_mask(disp, 0x610090, 0x00000001 << chid, 0x00000000); + nv_mask(disp, 0x6100a0, 0x00000001 << chid, 0x00000000); return nv50_disp_chan_fini(&dmac->base, suspend); } @@ -292,7 +292,7 @@ gf110_disp_core_mthd_chan = { static int gf110_disp_core_init(struct nvkm_object *object) { - struct nv50_disp_priv *priv = (void *)object->engine; + struct nv50_disp *disp = (void *)object->engine; struct nv50_disp_dmac *mast = (void *)object; int ret; @@ -301,19 +301,19 @@ gf110_disp_core_init(struct nvkm_object *object) return ret; /* enable error reporting */ - nv_mask(priv, 0x6100a0, 0x00000001, 0x00000001); + nv_mask(disp, 0x6100a0, 0x00000001, 0x00000001); /* initialise channel for dma command submission */ - nv_wr32(priv, 0x610494, mast->push); - nv_wr32(priv, 0x610498, 0x00010000); - nv_wr32(priv, 0x61049c, 0x00000001); - nv_mask(priv, 0x610490, 0x00000010, 0x00000010); - nv_wr32(priv, 0x640000, 0x00000000); - nv_wr32(priv, 0x610490, 0x01000013); + nv_wr32(disp, 0x610494, mast->push); + nv_wr32(disp, 0x610498, 0x00010000); + nv_wr32(disp, 0x61049c, 0x00000001); + nv_mask(disp, 0x610490, 0x00000010, 0x00000010); + nv_wr32(disp, 0x640000, 0x00000000); + nv_wr32(disp, 0x610490, 0x01000013); /* wait for it to go inactive */ - if (!nv_wait(priv, 0x610490, 0x80000000, 0x00000000)) { - nv_error(mast, "init: 0x%08x\n", nv_rd32(priv, 0x610490)); + if (!nv_wait(disp, 0x610490, 0x80000000, 0x00000000)) { + nv_error(mast, "init: 0x%08x\n", nv_rd32(disp, 0x610490)); return -EBUSY; } @@ -323,21 +323,21 @@ gf110_disp_core_init(struct nvkm_object *object) static int gf110_disp_core_fini(struct nvkm_object *object, bool suspend) { - struct nv50_disp_priv *priv = (void *)object->engine; + struct nv50_disp *disp = (void *)object->engine; struct nv50_disp_dmac *mast = (void *)object; /* deactivate channel */ - nv_mask(priv, 0x610490, 0x00000010, 0x00000000); - nv_mask(priv, 0x610490, 0x00000003, 0x00000000); - if (!nv_wait(priv, 0x610490, 0x001e0000, 0x00000000)) { - nv_error(mast, "fini: 0x%08x\n", nv_rd32(priv, 0x610490)); + nv_mask(disp, 0x610490, 0x00000010, 0x00000000); + nv_mask(disp, 0x610490, 0x00000003, 0x00000000); + if (!nv_wait(disp, 0x610490, 0x001e0000, 0x00000000)) { + nv_error(mast, "fini: 0x%08x\n", nv_rd32(disp, 0x610490)); if (suspend) return -EBUSY; } /* disable error reporting and completion notification */ - nv_mask(priv, 0x610090, 0x00000001, 0x00000000); - nv_mask(priv, 0x6100a0, 0x00000001, 0x00000000); + nv_mask(disp, 0x610090, 0x00000001, 0x00000000); + nv_mask(disp, 0x6100a0, 0x00000001, 0x00000000); return nv50_disp_chan_fini(&mast->base, suspend); } @@ -539,7 +539,7 @@ gf110_disp_ovly_ofuncs = { static int gf110_disp_pioc_init(struct nvkm_object *object) { - struct nv50_disp_priv *priv = (void *)object->engine; + struct nv50_disp *disp = (void *)object->engine; struct nv50_disp_pioc *pioc = (void *)object; int chid = pioc->base.chid; int ret; @@ -549,13 +549,13 @@ gf110_disp_pioc_init(struct nvkm_object *object) return ret; /* enable error reporting */ - nv_mask(priv, 0x6100a0, 0x00000001 << chid, 0x00000001 << chid); + nv_mask(disp, 0x6100a0, 0x00000001 << chid, 0x00000001 << chid); /* activate channel */ - nv_wr32(priv, 0x610490 + (chid * 0x10), 0x00000001); - if (!nv_wait(priv, 0x610490 + (chid * 0x10), 0x00030000, 0x00010000)) { + nv_wr32(disp, 0x610490 + (chid * 0x10), 0x00000001); + if (!nv_wait(disp, 0x610490 + (chid * 0x10), 0x00030000, 0x00010000)) { nv_error(pioc, "init: 0x%08x\n", - nv_rd32(priv, 0x610490 + (chid * 0x10))); + nv_rd32(disp, 0x610490 + (chid * 0x10))); return -EBUSY; } @@ -565,21 +565,21 @@ gf110_disp_pioc_init(struct nvkm_object *object) static int gf110_disp_pioc_fini(struct nvkm_object *object, bool suspend) { - struct nv50_disp_priv *priv = (void *)object->engine; + struct nv50_disp *disp = (void *)object->engine; struct nv50_disp_pioc *pioc = (void *)object; int chid = pioc->base.chid; - nv_mask(priv, 0x610490 + (chid * 0x10), 0x00000001, 0x00000000); - if (!nv_wait(priv, 0x610490 + (chid * 0x10), 0x00030000, 0x00000000)) { + nv_mask(disp, 0x610490 + (chid * 0x10), 0x00000001, 0x00000000); + if (!nv_wait(disp, 0x610490 + (chid * 0x10), 0x00030000, 0x00000000)) { nv_error(pioc, "timeout: 0x%08x\n", - nv_rd32(priv, 0x610490 + (chid * 0x10))); + nv_rd32(disp, 0x610490 + (chid * 0x10))); if (suspend) return -EBUSY; } /* disable error reporting and completion notification */ - nv_mask(priv, 0x610090, 0x00000001 << chid, 0x00000000); - nv_mask(priv, 0x6100a0, 0x00000001 << chid, 0x00000000); + nv_mask(disp, 0x610090, 0x00000001 << chid, 0x00000000); + nv_mask(disp, 0x6100a0, 0x00000001 << chid, 0x00000000); return nv50_disp_chan_fini(&pioc->base, suspend); } @@ -625,9 +625,9 @@ gf110_disp_curs_ofuncs = { int gf110_disp_main_scanoutpos(NV50_DISP_MTHD_V0) { - const u32 total = nv_rd32(priv, 0x640414 + (head * 0x300)); - const u32 blanke = nv_rd32(priv, 0x64041c + (head * 0x300)); - const u32 blanks = nv_rd32(priv, 0x640420 + (head * 0x300)); + const u32 total = nv_rd32(disp, 0x640414 + (head * 0x300)); + const u32 blanke = nv_rd32(disp, 0x64041c + (head * 0x300)); + const u32 blanks = nv_rd32(disp, 0x640420 + (head * 0x300)); union { struct nv04_disp_scanoutpos_v0 v0; } *args = data; @@ -644,10 +644,10 @@ gf110_disp_main_scanoutpos(NV50_DISP_MTHD_V0) args->v0.htotal = ( total & 0x0000ffff); args->v0.time[0] = ktime_to_ns(ktime_get()); args->v0.vline = /* vline read locks hline */ - nv_rd32(priv, 0x616340 + (head * 0x800)) & 0xffff; + nv_rd32(disp, 0x616340 + (head * 0x800)) & 0xffff; args->v0.time[1] = ktime_to_ns(ktime_get()); args->v0.hline = - nv_rd32(priv, 0x616344 + (head * 0x800)) & 0xffff; + nv_rd32(disp, 0x616344 + (head * 0x800)) & 0xffff; } else return ret; @@ -657,7 +657,7 @@ gf110_disp_main_scanoutpos(NV50_DISP_MTHD_V0) static int gf110_disp_main_init(struct nvkm_object *object) { - struct nv50_disp_priv *priv = (void *)object->engine; + struct nv50_disp *disp = (void *)object->engine; struct nv50_disp_base *base = (void *)object; int ret, i; u32 tmp; @@ -672,44 +672,44 @@ gf110_disp_main_init(struct nvkm_object *object) */ /* ... CRTC caps */ - for (i = 0; i < priv->head.nr; i++) { - tmp = nv_rd32(priv, 0x616104 + (i * 0x800)); - nv_wr32(priv, 0x6101b4 + (i * 0x800), tmp); - tmp = nv_rd32(priv, 0x616108 + (i * 0x800)); - nv_wr32(priv, 0x6101b8 + (i * 0x800), tmp); - tmp = nv_rd32(priv, 0x61610c + (i * 0x800)); - nv_wr32(priv, 0x6101bc + (i * 0x800), tmp); + for (i = 0; i < disp->head.nr; i++) { + tmp = nv_rd32(disp, 0x616104 + (i * 0x800)); + nv_wr32(disp, 0x6101b4 + (i * 0x800), tmp); + tmp = nv_rd32(disp, 0x616108 + (i * 0x800)); + nv_wr32(disp, 0x6101b8 + (i * 0x800), tmp); + tmp = nv_rd32(disp, 0x61610c + (i * 0x800)); + nv_wr32(disp, 0x6101bc + (i * 0x800), tmp); } /* ... DAC caps */ - for (i = 0; i < priv->dac.nr; i++) { - tmp = nv_rd32(priv, 0x61a000 + (i * 0x800)); - nv_wr32(priv, 0x6101c0 + (i * 0x800), tmp); + for (i = 0; i < disp->dac.nr; i++) { + tmp = nv_rd32(disp, 0x61a000 + (i * 0x800)); + nv_wr32(disp, 0x6101c0 + (i * 0x800), tmp); } /* ... SOR caps */ - for (i = 0; i < priv->sor.nr; i++) { - tmp = nv_rd32(priv, 0x61c000 + (i * 0x800)); - nv_wr32(priv, 0x6301c4 + (i * 0x800), tmp); + for (i = 0; i < disp->sor.nr; i++) { + tmp = nv_rd32(disp, 0x61c000 + (i * 0x800)); + nv_wr32(disp, 0x6301c4 + (i * 0x800), tmp); } /* steal display away from vbios, or something like that */ - if (nv_rd32(priv, 0x6100ac) & 0x00000100) { - nv_wr32(priv, 0x6100ac, 0x00000100); - nv_mask(priv, 0x6194e8, 0x00000001, 0x00000000); - if (!nv_wait(priv, 0x6194e8, 0x00000002, 0x00000000)) { - nv_error(priv, "timeout acquiring display\n"); + if (nv_rd32(disp, 0x6100ac) & 0x00000100) { + nv_wr32(disp, 0x6100ac, 0x00000100); + nv_mask(disp, 0x6194e8, 0x00000001, 0x00000000); + if (!nv_wait(disp, 0x6194e8, 0x00000002, 0x00000000)) { + nv_error(disp, "timeout acquiring display\n"); return -EBUSY; } } /* point at display engine memory area (hash table, objects) */ - nv_wr32(priv, 0x610010, (nv_gpuobj(object->parent)->addr >> 8) | 9); + nv_wr32(disp, 0x610010, (nv_gpuobj(object->parent)->addr >> 8) | 9); /* enable supervisor interrupts, disable everything else */ - nv_wr32(priv, 0x610090, 0x00000000); - nv_wr32(priv, 0x6100a0, 0x00000000); - nv_wr32(priv, 0x6100b0, 0x00000307); + nv_wr32(disp, 0x610090, 0x00000000); + nv_wr32(disp, 0x6100a0, 0x00000000); + nv_wr32(disp, 0x6100b0, 0x00000307); /* disable underflow reporting, preventing an intermittent issue * on some gk104 boards where the production vbios left this @@ -717,8 +717,8 @@ gf110_disp_main_init(struct nvkm_object *object) * * ftp://download.nvidia.com/open-gpu-doc/gk104-disable-underflow-reporting/1/gk104-disable-underflow-reporting.txt */ - for (i = 0; i < priv->head.nr; i++) - nv_mask(priv, 0x616308 + (i * 0x800), 0x00000111, 0x00000010); + for (i = 0; i < disp->head.nr; i++) + nv_mask(disp, 0x616308 + (i * 0x800), 0x00000111, 0x00000010); return 0; } @@ -726,11 +726,11 @@ gf110_disp_main_init(struct nvkm_object *object) static int gf110_disp_main_fini(struct nvkm_object *object, bool suspend) { - struct nv50_disp_priv *priv = (void *)object->engine; + struct nv50_disp *disp = (void *)object->engine; struct nv50_disp_base *base = (void *)object; /* disable all interrupts */ - nv_wr32(priv, 0x6100b0, 0x00000000); + nv_wr32(disp, 0x6100b0, 0x00000000); return nvkm_parent_fini(&base->base, suspend); } @@ -787,11 +787,11 @@ gf110_disp_vblank_func = { }; static struct nvkm_output * -exec_lookup(struct nv50_disp_priv *priv, int head, int or, u32 ctrl, +exec_lookup(struct nv50_disp *disp, int head, int or, u32 ctrl, u32 *data, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_outp *info) { - struct nvkm_bios *bios = nvkm_bios(priv); + struct nvkm_bios *bios = nvkm_bios(disp); struct nvkm_output *outp; u16 mask, type; @@ -808,7 +808,7 @@ exec_lookup(struct nv50_disp_priv *priv, int head, int or, u32 ctrl, case 0x00000800: type = DCB_OUTPUT_DP; mask = 1; break; case 0x00000900: type = DCB_OUTPUT_DP; mask = 2; break; default: - nv_error(priv, "unknown SOR mc 0x%08x\n", ctrl); + nv_error(disp, "unknown SOR mc 0x%08x\n", ctrl); return NULL; } } @@ -817,7 +817,7 @@ exec_lookup(struct nv50_disp_priv *priv, int head, int or, u32 ctrl, mask |= 0x0001 << or; mask |= 0x0100 << head; - list_for_each_entry(outp, &priv->base.outp, head) { + list_for_each_entry(outp, &disp->base.outp, head) { if ((outp->info.hasht & 0xff) == type && (outp->info.hashm & mask) == mask) { *data = nvbios_outp_match(bios, outp->info.hasht, @@ -833,9 +833,9 @@ exec_lookup(struct nv50_disp_priv *priv, int head, int or, u32 ctrl, } static struct nvkm_output * -exec_script(struct nv50_disp_priv *priv, int head, int id) +exec_script(struct nv50_disp *disp, int head, int id) { - struct nvkm_bios *bios = nvkm_bios(priv); + struct nvkm_bios *bios = nvkm_bios(disp); struct nvkm_output *outp; struct nvbios_outp info; u8 ver, hdr, cnt, len; @@ -843,7 +843,7 @@ exec_script(struct nv50_disp_priv *priv, int head, int id) int or; for (or = 0; !(ctrl & (1 << head)) && or < 8; or++) { - ctrl = nv_rd32(priv, 0x640180 + (or * 0x20)); + ctrl = nv_rd32(disp, 0x640180 + (or * 0x20)); if (ctrl & (1 << head)) break; } @@ -851,10 +851,10 @@ exec_script(struct nv50_disp_priv *priv, int head, int id) if (or == 8) return NULL; - outp = exec_lookup(priv, head, or, ctrl, &data, &ver, &hdr, &cnt, &len, &info); + outp = exec_lookup(disp, head, or, ctrl, &data, &ver, &hdr, &cnt, &len, &info); if (outp) { struct nvbios_init init = { - .subdev = nv_subdev(priv), + .subdev = nv_subdev(disp), .bios = bios, .offset = info.script[id], .outp = &outp->info, @@ -869,9 +869,9 @@ exec_script(struct nv50_disp_priv *priv, int head, int id) } static struct nvkm_output * -exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk, u32 *conf) +exec_clkcmp(struct nv50_disp *disp, int head, int id, u32 pclk, u32 *conf) { - struct nvkm_bios *bios = nvkm_bios(priv); + struct nvkm_bios *bios = nvkm_bios(disp); struct nvkm_output *outp; struct nvbios_outp info1; struct nvbios_ocfg info2; @@ -880,7 +880,7 @@ exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk, u32 *conf) int or; for (or = 0; !(ctrl & (1 << head)) && or < 8; or++) { - ctrl = nv_rd32(priv, 0x660180 + (or * 0x20)); + ctrl = nv_rd32(disp, 0x660180 + (or * 0x20)); if (ctrl & (1 << head)) break; } @@ -888,7 +888,7 @@ exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk, u32 *conf) if (or == 8) return NULL; - outp = exec_lookup(priv, head, or, ctrl, &data, &ver, &hdr, &cnt, &len, &info1); + outp = exec_lookup(disp, head, or, ctrl, &data, &ver, &hdr, &cnt, &len, &info1); if (!outp) return NULL; @@ -899,7 +899,7 @@ exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk, u32 *conf) *conf |= 0x0100; break; case DCB_OUTPUT_LVDS: - *conf = priv->sor.lvdsconf; + *conf = disp->sor.lvdsconf; break; case DCB_OUTPUT_DP: *conf = (ctrl & 0x00000f00) >> 8; @@ -915,7 +915,7 @@ exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk, u32 *conf) data = nvbios_oclk_match(bios, info2.clkcmp[id], pclk); if (data) { struct nvbios_init init = { - .subdev = nv_subdev(priv), + .subdev = nv_subdev(disp), .bios = bios, .offset = data, .outp = &outp->info, @@ -931,22 +931,22 @@ exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk, u32 *conf) } static void -gf110_disp_intr_unk1_0(struct nv50_disp_priv *priv, int head) +gf110_disp_intr_unk1_0(struct nv50_disp *disp, int head) { - exec_script(priv, head, 1); + exec_script(disp, head, 1); } static void -gf110_disp_intr_unk2_0(struct nv50_disp_priv *priv, int head) +gf110_disp_intr_unk2_0(struct nv50_disp *disp, int head) { - struct nvkm_output *outp = exec_script(priv, head, 2); + struct nvkm_output *outp = exec_script(disp, head, 2); /* see note in nv50_disp_intr_unk20_0() */ if (outp && outp->info.type == DCB_OUTPUT_DP) { struct nvkm_output_dp *outpdp = (void *)outp; struct nvbios_init init = { - .subdev = nv_subdev(priv), - .bios = nvkm_bios(priv), + .subdev = nv_subdev(disp), + .bios = nvkm_bios(disp), .outp = &outp->info, .crtc = head, .offset = outpdp->info.script[4], @@ -959,34 +959,34 @@ gf110_disp_intr_unk2_0(struct nv50_disp_priv *priv, int head) } static void -gf110_disp_intr_unk2_1(struct nv50_disp_priv *priv, int head) +gf110_disp_intr_unk2_1(struct nv50_disp *disp, int head) { - struct nvkm_devinit *devinit = nvkm_devinit(priv); - u32 pclk = nv_rd32(priv, 0x660450 + (head * 0x300)) / 1000; + struct nvkm_devinit *devinit = nvkm_devinit(disp); + u32 pclk = nv_rd32(disp, 0x660450 + (head * 0x300)) / 1000; if (pclk) devinit->pll_set(devinit, PLL_VPLL0 + head, pclk); - nv_wr32(priv, 0x612200 + (head * 0x800), 0x00000000); + nv_wr32(disp, 0x612200 + (head * 0x800), 0x00000000); } static void -gf110_disp_intr_unk2_2_tu(struct nv50_disp_priv *priv, int head, +gf110_disp_intr_unk2_2_tu(struct nv50_disp *disp, int head, struct dcb_output *outp) { const int or = ffs(outp->or) - 1; - const u32 ctrl = nv_rd32(priv, 0x660200 + (or * 0x020)); - const u32 conf = nv_rd32(priv, 0x660404 + (head * 0x300)); - const s32 vactive = nv_rd32(priv, 0x660414 + (head * 0x300)) & 0xffff; - const s32 vblanke = nv_rd32(priv, 0x66041c + (head * 0x300)) & 0xffff; - const s32 vblanks = nv_rd32(priv, 0x660420 + (head * 0x300)) & 0xffff; - const u32 pclk = nv_rd32(priv, 0x660450 + (head * 0x300)) / 1000; + const u32 ctrl = nv_rd32(disp, 0x660200 + (or * 0x020)); + const u32 conf = nv_rd32(disp, 0x660404 + (head * 0x300)); + const s32 vactive = nv_rd32(disp, 0x660414 + (head * 0x300)) & 0xffff; + const s32 vblanke = nv_rd32(disp, 0x66041c + (head * 0x300)) & 0xffff; + const s32 vblanks = nv_rd32(disp, 0x660420 + (head * 0x300)) & 0xffff; + const u32 pclk = nv_rd32(disp, 0x660450 + (head * 0x300)) / 1000; const u32 link = ((ctrl & 0xf00) == 0x800) ? 0 : 1; const u32 hoff = (head * 0x800); const u32 soff = ( or * 0x800); const u32 loff = (link * 0x080) + soff; const u32 symbol = 100000; const u32 TU = 64; - u32 dpctrl = nv_rd32(priv, 0x61c10c + loff); - u32 clksor = nv_rd32(priv, 0x612300 + soff); + u32 dpctrl = nv_rd32(disp, 0x61c10c + loff); + u32 clksor = nv_rd32(disp, 0x612300 + soff); u32 datarate, link_nr, link_bw, bits; u64 ratio, value; @@ -999,14 +999,14 @@ gf110_disp_intr_unk2_2_tu(struct nv50_disp_priv *priv, int head, value = value * link_bw; do_div(value, pclk); value = value - (3 * !!(dpctrl & 0x00004000)) - (12 / link_nr); - nv_mask(priv, 0x616620 + hoff, 0x0000ffff, value); + nv_mask(disp, 0x616620 + hoff, 0x0000ffff, value); /* symbols/vblank - algorithm taken from comments in tegra driver */ value = vblanks - vblanke - 25; value = value * link_bw; do_div(value, pclk); value = value - ((36 / link_nr) + 3) - 1; - nv_mask(priv, 0x616624 + hoff, 0x00ffffff, value); + nv_mask(disp, 0x616624 + hoff, 0x00ffffff, value); /* watermark */ if ((conf & 0x3c0) == 0x180) bits = 30; @@ -1026,23 +1026,23 @@ gf110_disp_intr_unk2_2_tu(struct nv50_disp_priv *priv, int head, value += 5; value |= 0x08000000; - nv_wr32(priv, 0x616610 + hoff, value); + nv_wr32(disp, 0x616610 + hoff, value); } static void -gf110_disp_intr_unk2_2(struct nv50_disp_priv *priv, int head) +gf110_disp_intr_unk2_2(struct nv50_disp *disp, int head) { struct nvkm_output *outp; - u32 pclk = nv_rd32(priv, 0x660450 + (head * 0x300)) / 1000; + u32 pclk = nv_rd32(disp, 0x660450 + (head * 0x300)) / 1000; u32 conf, addr, data; - outp = exec_clkcmp(priv, head, 0xff, pclk, &conf); + outp = exec_clkcmp(disp, head, 0xff, pclk, &conf); if (!outp) return; /* see note in nv50_disp_intr_unk20_2() */ if (outp->info.type == DCB_OUTPUT_DP) { - u32 sync = nv_rd32(priv, 0x660404 + (head * 0x300)); + u32 sync = nv_rd32(disp, 0x660404 + (head * 0x300)); switch ((sync & 0x000003c0) >> 6) { case 6: pclk = pclk * 30; break; case 5: pclk = pclk * 24; break; @@ -1055,11 +1055,11 @@ gf110_disp_intr_unk2_2(struct nv50_disp_priv *priv, int head) if (nvkm_output_dp_train(outp, pclk, true)) ERR("link not trained before attach\n"); } else { - if (priv->sor.magic) - priv->sor.magic(outp); + if (disp->sor.magic) + disp->sor.magic(outp); } - exec_clkcmp(priv, head, 0, pclk, &conf); + exec_clkcmp(disp, head, 0, pclk, &conf); if (outp->info.type == DCB_OUTPUT_ANALOG) { addr = 0x612280 + (ffs(outp->info.or) - 1) * 0x800; @@ -1069,102 +1069,102 @@ gf110_disp_intr_unk2_2(struct nv50_disp_priv *priv, int head) data = (conf & 0x0100) ? 0x00000101 : 0x00000000; switch (outp->info.type) { case DCB_OUTPUT_TMDS: - nv_mask(priv, addr, 0x007c0000, 0x00280000); + nv_mask(disp, addr, 0x007c0000, 0x00280000); break; case DCB_OUTPUT_DP: - gf110_disp_intr_unk2_2_tu(priv, head, &outp->info); + gf110_disp_intr_unk2_2_tu(disp, head, &outp->info); break; default: break; } } - nv_mask(priv, addr, 0x00000707, data); + nv_mask(disp, addr, 0x00000707, data); } static void -gf110_disp_intr_unk4_0(struct nv50_disp_priv *priv, int head) +gf110_disp_intr_unk4_0(struct nv50_disp *disp, int head) { - u32 pclk = nv_rd32(priv, 0x660450 + (head * 0x300)) / 1000; + u32 pclk = nv_rd32(disp, 0x660450 + (head * 0x300)) / 1000; u32 conf; - exec_clkcmp(priv, head, 1, pclk, &conf); + exec_clkcmp(disp, head, 1, pclk, &conf); } void gf110_disp_intr_supervisor(struct work_struct *work) { - struct nv50_disp_priv *priv = - container_of(work, struct nv50_disp_priv, supervisor); - struct nv50_disp_impl *impl = (void *)nv_object(priv)->oclass; + struct nv50_disp *disp = + container_of(work, struct nv50_disp, supervisor); + struct nv50_disp_impl *impl = (void *)nv_object(disp)->oclass; u32 mask[4]; int head; - nv_debug(priv, "supervisor %d\n", ffs(priv->super)); - for (head = 0; head < priv->head.nr; head++) { - mask[head] = nv_rd32(priv, 0x6101d4 + (head * 0x800)); - nv_debug(priv, "head %d: 0x%08x\n", head, mask[head]); + nv_debug(disp, "supervisor %d\n", ffs(disp->super)); + for (head = 0; head < disp->head.nr; head++) { + mask[head] = nv_rd32(disp, 0x6101d4 + (head * 0x800)); + nv_debug(disp, "head %d: 0x%08x\n", head, mask[head]); } - if (priv->super & 0x00000001) { - nv50_disp_mthd_chan(priv, NV_DBG_DEBUG, 0, impl->mthd.core); - for (head = 0; head < priv->head.nr; head++) { + if (disp->super & 0x00000001) { + nv50_disp_mthd_chan(disp, NV_DBG_DEBUG, 0, impl->mthd.core); + for (head = 0; head < disp->head.nr; head++) { if (!(mask[head] & 0x00001000)) continue; - nv_debug(priv, "supervisor 1.0 - head %d\n", head); - gf110_disp_intr_unk1_0(priv, head); + nv_debug(disp, "supervisor 1.0 - head %d\n", head); + gf110_disp_intr_unk1_0(disp, head); } } else - if (priv->super & 0x00000002) { - for (head = 0; head < priv->head.nr; head++) { + if (disp->super & 0x00000002) { + for (head = 0; head < disp->head.nr; head++) { if (!(mask[head] & 0x00001000)) continue; - nv_debug(priv, "supervisor 2.0 - head %d\n", head); - gf110_disp_intr_unk2_0(priv, head); + nv_debug(disp, "supervisor 2.0 - head %d\n", head); + gf110_disp_intr_unk2_0(disp, head); } - for (head = 0; head < priv->head.nr; head++) { + for (head = 0; head < disp->head.nr; head++) { if (!(mask[head] & 0x00010000)) continue; - nv_debug(priv, "supervisor 2.1 - head %d\n", head); - gf110_disp_intr_unk2_1(priv, head); + nv_debug(disp, "supervisor 2.1 - head %d\n", head); + gf110_disp_intr_unk2_1(disp, head); } - for (head = 0; head < priv->head.nr; head++) { + for (head = 0; head < disp->head.nr; head++) { if (!(mask[head] & 0x00001000)) continue; - nv_debug(priv, "supervisor 2.2 - head %d\n", head); - gf110_disp_intr_unk2_2(priv, head); + nv_debug(disp, "supervisor 2.2 - head %d\n", head); + gf110_disp_intr_unk2_2(disp, head); } } else - if (priv->super & 0x00000004) { - for (head = 0; head < priv->head.nr; head++) { + if (disp->super & 0x00000004) { + for (head = 0; head < disp->head.nr; head++) { if (!(mask[head] & 0x00001000)) continue; - nv_debug(priv, "supervisor 3.0 - head %d\n", head); - gf110_disp_intr_unk4_0(priv, head); + nv_debug(disp, "supervisor 3.0 - head %d\n", head); + gf110_disp_intr_unk4_0(disp, head); } } - for (head = 0; head < priv->head.nr; head++) - nv_wr32(priv, 0x6101d4 + (head * 0x800), 0x00000000); - nv_wr32(priv, 0x6101d0, 0x80000000); + for (head = 0; head < disp->head.nr; head++) + nv_wr32(disp, 0x6101d4 + (head * 0x800), 0x00000000); + nv_wr32(disp, 0x6101d0, 0x80000000); } static void -gf110_disp_intr_error(struct nv50_disp_priv *priv, int chid) +gf110_disp_intr_error(struct nv50_disp *disp, int chid) { - const struct nv50_disp_impl *impl = (void *)nv_object(priv)->oclass; - u32 mthd = nv_rd32(priv, 0x6101f0 + (chid * 12)); - u32 data = nv_rd32(priv, 0x6101f4 + (chid * 12)); - u32 unkn = nv_rd32(priv, 0x6101f8 + (chid * 12)); + const struct nv50_disp_impl *impl = (void *)nv_object(disp)->oclass; + u32 mthd = nv_rd32(disp, 0x6101f0 + (chid * 12)); + u32 data = nv_rd32(disp, 0x6101f4 + (chid * 12)); + u32 unkn = nv_rd32(disp, 0x6101f8 + (chid * 12)); - nv_error(priv, "chid %d mthd 0x%04x data 0x%08x " + nv_error(disp, "chid %d mthd 0x%04x data 0x%08x " "0x%08x 0x%08x\n", chid, (mthd & 0x0000ffc), data, mthd, unkn); if (chid == 0) { switch (mthd & 0xffc) { case 0x0080: - nv50_disp_mthd_chan(priv, NV_DBG_ERROR, chid - 0, + nv50_disp_mthd_chan(disp, NV_DBG_ERROR, chid - 0, impl->mthd.core); break; default: @@ -1174,7 +1174,7 @@ gf110_disp_intr_error(struct nv50_disp_priv *priv, int chid) if (chid <= 4) { switch (mthd & 0xffc) { case 0x0080: - nv50_disp_mthd_chan(priv, NV_DBG_ERROR, chid - 1, + nv50_disp_mthd_chan(disp, NV_DBG_ERROR, chid - 1, impl->mthd.base); break; default: @@ -1184,7 +1184,7 @@ gf110_disp_intr_error(struct nv50_disp_priv *priv, int chid) if (chid <= 8) { switch (mthd & 0xffc) { case 0x0080: - nv50_disp_mthd_chan(priv, NV_DBG_ERROR, chid - 5, + nv50_disp_mthd_chan(disp, NV_DBG_ERROR, chid - 5, impl->mthd.ovly); break; default: @@ -1192,60 +1192,60 @@ gf110_disp_intr_error(struct nv50_disp_priv *priv, int chid) } } - nv_wr32(priv, 0x61009c, (1 << chid)); - nv_wr32(priv, 0x6101f0 + (chid * 12), 0x90000000); + nv_wr32(disp, 0x61009c, (1 << chid)); + nv_wr32(disp, 0x6101f0 + (chid * 12), 0x90000000); } void gf110_disp_intr(struct nvkm_subdev *subdev) { - struct nv50_disp_priv *priv = (void *)subdev; - u32 intr = nv_rd32(priv, 0x610088); + struct nv50_disp *disp = (void *)subdev; + u32 intr = nv_rd32(disp, 0x610088); int i; if (intr & 0x00000001) { - u32 stat = nv_rd32(priv, 0x61008c); + u32 stat = nv_rd32(disp, 0x61008c); while (stat) { int chid = __ffs(stat); stat &= ~(1 << chid); - nv50_disp_chan_uevent_send(priv, chid); - nv_wr32(priv, 0x61008c, 1 << chid); + nv50_disp_chan_uevent_send(disp, chid); + nv_wr32(disp, 0x61008c, 1 << chid); } intr &= ~0x00000001; } if (intr & 0x00000002) { - u32 stat = nv_rd32(priv, 0x61009c); + u32 stat = nv_rd32(disp, 0x61009c); int chid = ffs(stat) - 1; if (chid >= 0) - gf110_disp_intr_error(priv, chid); + gf110_disp_intr_error(disp, chid); intr &= ~0x00000002; } if (intr & 0x00100000) { - u32 stat = nv_rd32(priv, 0x6100ac); + u32 stat = nv_rd32(disp, 0x6100ac); if (stat & 0x00000007) { - priv->super = (stat & 0x00000007); - schedule_work(&priv->supervisor); - nv_wr32(priv, 0x6100ac, priv->super); + disp->super = (stat & 0x00000007); + schedule_work(&disp->supervisor); + nv_wr32(disp, 0x6100ac, disp->super); stat &= ~0x00000007; } if (stat) { - nv_info(priv, "unknown intr24 0x%08x\n", stat); - nv_wr32(priv, 0x6100ac, stat); + nv_info(disp, "unknown intr24 0x%08x\n", stat); + nv_wr32(disp, 0x6100ac, stat); } intr &= ~0x00100000; } - for (i = 0; i < priv->head.nr; i++) { + for (i = 0; i < disp->head.nr; i++) { u32 mask = 0x01000000 << i; if (mask & intr) { - u32 stat = nv_rd32(priv, 0x6100bc + (i * 0x800)); + u32 stat = nv_rd32(disp, 0x6100bc + (i * 0x800)); if (stat & 0x00000001) - nvkm_disp_vblank(&priv->base, i); - nv_mask(priv, 0x6100bc + (i * 0x800), 0, 0); - nv_rd32(priv, 0x6100c0 + (i * 0x800)); + nvkm_disp_vblank(&disp->base, i); + nv_mask(disp, 0x6100bc + (i * 0x800), 0, 0); + nv_rd32(disp, 0x6100c0 + (i * 0x800)); } } } @@ -1255,33 +1255,33 @@ gf110_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nv50_disp_priv *priv; + struct nv50_disp *disp; int heads = nv_rd32(parent, 0x022448); int ret; ret = nvkm_disp_create(parent, engine, oclass, heads, - "PDISP", "display", &priv); - *pobject = nv_object(priv); + "PDISP", "display", &disp); + *pobject = nv_object(disp); if (ret) return ret; - ret = nvkm_event_init(&gf110_disp_chan_uevent, 1, 17, &priv->uevent); + ret = nvkm_event_init(&gf110_disp_chan_uevent, 1, 17, &disp->uevent); if (ret) return ret; - nv_engine(priv)->sclass = gf110_disp_main_oclass; - nv_engine(priv)->cclass = &nv50_disp_cclass; - nv_subdev(priv)->intr = gf110_disp_intr; - INIT_WORK(&priv->supervisor, gf110_disp_intr_supervisor); - priv->sclass = gf110_disp_sclass; - priv->head.nr = heads; - priv->dac.nr = 3; - priv->sor.nr = 4; - priv->dac.power = nv50_dac_power; - priv->dac.sense = nv50_dac_sense; - priv->sor.power = nv50_sor_power; - priv->sor.hda_eld = gf110_hda_eld; - priv->sor.hdmi = gf110_hdmi_ctrl; + nv_engine(disp)->sclass = gf110_disp_main_oclass; + nv_engine(disp)->cclass = &nv50_disp_cclass; + nv_subdev(disp)->intr = gf110_disp_intr; + INIT_WORK(&disp->supervisor, gf110_disp_intr_supervisor); + disp->sclass = gf110_disp_sclass; + disp->head.nr = heads; + disp->dac.nr = 3; + disp->sor.nr = 4; + disp->dac.power = nv50_dac_power; + disp->dac.sense = nv50_dac_sense; + disp->sor.power = nv50_sor_power; + disp->sor.hda_eld = gf110_hda_eld; + disp->sor.hdmi = gf110_hdmi_ctrl; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c index 6f4019ab4e65..ccb5bfad9ec8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c @@ -219,33 +219,33 @@ gk104_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nv50_disp_priv *priv; + struct nv50_disp *disp; int heads = nv_rd32(parent, 0x022448); int ret; ret = nvkm_disp_create(parent, engine, oclass, heads, - "PDISP", "display", &priv); - *pobject = nv_object(priv); + "PDISP", "display", &disp); + *pobject = nv_object(disp); if (ret) return ret; - ret = nvkm_event_init(&gf110_disp_chan_uevent, 1, 17, &priv->uevent); + ret = nvkm_event_init(&gf110_disp_chan_uevent, 1, 17, &disp->uevent); if (ret) return ret; - nv_engine(priv)->sclass = gk104_disp_main_oclass; - nv_engine(priv)->cclass = &nv50_disp_cclass; - nv_subdev(priv)->intr = gf110_disp_intr; - INIT_WORK(&priv->supervisor, gf110_disp_intr_supervisor); - priv->sclass = gk104_disp_sclass; - priv->head.nr = heads; - priv->dac.nr = 3; - priv->sor.nr = 4; - priv->dac.power = nv50_dac_power; - priv->dac.sense = nv50_dac_sense; - priv->sor.power = nv50_sor_power; - priv->sor.hda_eld = gf110_hda_eld; - priv->sor.hdmi = gk104_hdmi_ctrl; + nv_engine(disp)->sclass = gk104_disp_main_oclass; + nv_engine(disp)->cclass = &nv50_disp_cclass; + nv_subdev(disp)->intr = gf110_disp_intr; + INIT_WORK(&disp->supervisor, gf110_disp_intr_supervisor); + disp->sclass = gk104_disp_sclass; + disp->head.nr = heads; + disp->dac.nr = 3; + disp->sor.nr = 4; + disp->dac.power = nv50_dac_power; + disp->dac.sense = nv50_dac_sense; + disp->sor.power = nv50_sor_power; + disp->sor.hda_eld = gf110_hda_eld; + disp->sor.hdmi = gk104_hdmi_ctrl; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.c index daa4b460a6ba..f4372fb38246 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.c @@ -54,33 +54,33 @@ gk110_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nv50_disp_priv *priv; + struct nv50_disp *disp; int heads = nv_rd32(parent, 0x022448); int ret; ret = nvkm_disp_create(parent, engine, oclass, heads, - "PDISP", "display", &priv); - *pobject = nv_object(priv); + "PDISP", "display", &disp); + *pobject = nv_object(disp); if (ret) return ret; - ret = nvkm_event_init(&gf110_disp_chan_uevent, 1, 17, &priv->uevent); + ret = nvkm_event_init(&gf110_disp_chan_uevent, 1, 17, &disp->uevent); if (ret) return ret; - nv_engine(priv)->sclass = gk110_disp_main_oclass; - nv_engine(priv)->cclass = &nv50_disp_cclass; - nv_subdev(priv)->intr = gf110_disp_intr; - INIT_WORK(&priv->supervisor, gf110_disp_intr_supervisor); - priv->sclass = gk110_disp_sclass; - priv->head.nr = heads; - priv->dac.nr = 3; - priv->sor.nr = 4; - priv->dac.power = nv50_dac_power; - priv->dac.sense = nv50_dac_sense; - priv->sor.power = nv50_sor_power; - priv->sor.hda_eld = gf110_hda_eld; - priv->sor.hdmi = gk104_hdmi_ctrl; + nv_engine(disp)->sclass = gk110_disp_main_oclass; + nv_engine(disp)->cclass = &nv50_disp_cclass; + nv_subdev(disp)->intr = gf110_disp_intr; + INIT_WORK(&disp->supervisor, gf110_disp_intr_supervisor); + disp->sclass = gk110_disp_sclass; + disp->head.nr = heads; + disp->dac.nr = 3; + disp->sor.nr = 4; + disp->dac.power = nv50_dac_power; + disp->dac.sense = nv50_dac_sense; + disp->sor.power = nv50_sor_power; + disp->sor.hda_eld = gf110_hda_eld; + disp->sor.hdmi = gk104_hdmi_ctrl; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c index 881cc94385a1..558c38736f55 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c @@ -54,33 +54,33 @@ gm107_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nv50_disp_priv *priv; + struct nv50_disp *disp; int heads = nv_rd32(parent, 0x022448); int ret; ret = nvkm_disp_create(parent, engine, oclass, heads, - "PDISP", "display", &priv); - *pobject = nv_object(priv); + "PDISP", "display", &disp); + *pobject = nv_object(disp); if (ret) return ret; - ret = nvkm_event_init(&gf110_disp_chan_uevent, 1, 17, &priv->uevent); + ret = nvkm_event_init(&gf110_disp_chan_uevent, 1, 17, &disp->uevent); if (ret) return ret; - nv_engine(priv)->sclass = gm107_disp_main_oclass; - nv_engine(priv)->cclass = &nv50_disp_cclass; - nv_subdev(priv)->intr = gf110_disp_intr; - INIT_WORK(&priv->supervisor, gf110_disp_intr_supervisor); - priv->sclass = gm107_disp_sclass; - priv->head.nr = heads; - priv->dac.nr = 3; - priv->sor.nr = 4; - priv->dac.power = nv50_dac_power; - priv->dac.sense = nv50_dac_sense; - priv->sor.power = nv50_sor_power; - priv->sor.hda_eld = gf110_hda_eld; - priv->sor.hdmi = gk104_hdmi_ctrl; + nv_engine(disp)->sclass = gm107_disp_main_oclass; + nv_engine(disp)->cclass = &nv50_disp_cclass; + nv_subdev(disp)->intr = gf110_disp_intr; + INIT_WORK(&disp->supervisor, gf110_disp_intr_supervisor); + disp->sclass = gm107_disp_sclass; + disp->head.nr = heads; + disp->dac.nr = 3; + disp->sor.nr = 4; + disp->dac.power = nv50_dac_power; + disp->dac.sense = nv50_dac_sense; + disp->sor.power = nv50_sor_power; + disp->sor.hda_eld = gf110_hda_eld; + disp->sor.hdmi = gk104_hdmi_ctrl; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm204.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm204.c index 67004f8302b3..a56ef7bd6623 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm204.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gm204.c @@ -55,34 +55,34 @@ gm204_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nv50_disp_priv *priv; + struct nv50_disp *disp; int heads = nv_rd32(parent, 0x022448); int ret; ret = nvkm_disp_create(parent, engine, oclass, heads, - "PDISP", "display", &priv); - *pobject = nv_object(priv); + "PDISP", "display", &disp); + *pobject = nv_object(disp); if (ret) return ret; - ret = nvkm_event_init(&gf110_disp_chan_uevent, 1, 17, &priv->uevent); + ret = nvkm_event_init(&gf110_disp_chan_uevent, 1, 17, &disp->uevent); if (ret) return ret; - nv_engine(priv)->sclass = gm204_disp_main_oclass; - nv_engine(priv)->cclass = &nv50_disp_cclass; - nv_subdev(priv)->intr = gf110_disp_intr; - INIT_WORK(&priv->supervisor, gf110_disp_intr_supervisor); - priv->sclass = gm204_disp_sclass; - priv->head.nr = heads; - priv->dac.nr = 3; - priv->sor.nr = 4; - priv->dac.power = nv50_dac_power; - priv->dac.sense = nv50_dac_sense; - priv->sor.power = nv50_sor_power; - priv->sor.hda_eld = gf110_hda_eld; - priv->sor.hdmi = gf110_hdmi_ctrl; - priv->sor.magic = gm204_sor_magic; + nv_engine(disp)->sclass = gm204_disp_main_oclass; + nv_engine(disp)->cclass = &nv50_disp_cclass; + nv_subdev(disp)->intr = gf110_disp_intr; + INIT_WORK(&disp->supervisor, gf110_disp_intr_supervisor); + disp->sclass = gm204_disp_sclass; + disp->head.nr = heads; + disp->dac.nr = 3; + disp->sor.nr = 4; + disp->dac.power = nv50_dac_power; + disp->dac.sense = nv50_dac_sense; + disp->sor.power = nv50_sor_power; + disp->sor.hda_eld = gf110_hda_eld; + disp->sor.hdmi = gf110_hdmi_ctrl; + disp->sor.magic = gm204_sor_magic; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gt200.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gt200.c index a45307213f4b..65cf51f3e8bd 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gt200.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gt200.c @@ -99,33 +99,33 @@ gt200_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nv50_disp_priv *priv; + struct nv50_disp *disp; int ret; ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP", - "display", &priv); - *pobject = nv_object(priv); + "display", &disp); + *pobject = nv_object(disp); if (ret) return ret; - ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent); + ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &disp->uevent); if (ret) return ret; - nv_engine(priv)->sclass = gt200_disp_main_oclass; - nv_engine(priv)->cclass = &nv50_disp_cclass; - nv_subdev(priv)->intr = nv50_disp_intr; - INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor); - priv->sclass = gt200_disp_sclass; - priv->head.nr = 2; - priv->dac.nr = 3; - priv->sor.nr = 2; - priv->pior.nr = 3; - priv->dac.power = nv50_dac_power; - priv->dac.sense = nv50_dac_sense; - priv->sor.power = nv50_sor_power; - priv->sor.hdmi = g84_hdmi_ctrl; - priv->pior.power = nv50_pior_power; + nv_engine(disp)->sclass = gt200_disp_main_oclass; + nv_engine(disp)->cclass = &nv50_disp_cclass; + nv_subdev(disp)->intr = nv50_disp_intr; + INIT_WORK(&disp->supervisor, nv50_disp_intr_supervisor); + disp->sclass = gt200_disp_sclass; + disp->head.nr = 2; + disp->dac.nr = 3; + disp->sor.nr = 2; + disp->pior.nr = 3; + disp->dac.power = nv50_dac_power; + disp->dac.sense = nv50_dac_sense; + disp->sor.power = nv50_sor_power; + disp->sor.hdmi = g84_hdmi_ctrl; + disp->pior.power = nv50_pior_power; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c index 55f0d3ac591e..0a2b794c3f63 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c @@ -54,34 +54,34 @@ gt215_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nv50_disp_priv *priv; + struct nv50_disp *disp; int ret; ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP", - "display", &priv); - *pobject = nv_object(priv); + "display", &disp); + *pobject = nv_object(disp); if (ret) return ret; - ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent); + ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &disp->uevent); if (ret) return ret; - nv_engine(priv)->sclass = gt215_disp_main_oclass; - nv_engine(priv)->cclass = &nv50_disp_cclass; - nv_subdev(priv)->intr = nv50_disp_intr; - INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor); - priv->sclass = gt215_disp_sclass; - priv->head.nr = 2; - priv->dac.nr = 3; - priv->sor.nr = 4; - priv->pior.nr = 3; - priv->dac.power = nv50_dac_power; - priv->dac.sense = nv50_dac_sense; - priv->sor.power = nv50_sor_power; - priv->sor.hda_eld = gt215_hda_eld; - priv->sor.hdmi = gt215_hdmi_ctrl; - priv->pior.power = nv50_pior_power; + nv_engine(disp)->sclass = gt215_disp_main_oclass; + nv_engine(disp)->cclass = &nv50_disp_cclass; + nv_subdev(disp)->intr = nv50_disp_intr; + INIT_WORK(&disp->supervisor, nv50_disp_intr_supervisor); + disp->sclass = gt215_disp_sclass; + disp->head.nr = 2; + disp->dac.nr = 3; + disp->sor.nr = 4; + disp->pior.nr = 3; + disp->dac.power = nv50_dac_power; + disp->dac.sense = nv50_dac_sense; + disp->sor.power = nv50_sor_power; + disp->sor.hda_eld = gt215_hda_eld; + disp->sor.hdmi = gt215_hdmi_ctrl; + disp->pior.power = nv50_pior_power; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagf110.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagf110.c index b9813d246ba5..fe07d7cb4dd7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagf110.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagf110.c @@ -52,21 +52,21 @@ gf110_hda_eld(NV50_DISP_MTHD_V1) if (size && args->v0.data[0]) { if (outp->info.type == DCB_OUTPUT_DP) { - nv_mask(priv, 0x616618 + hoff, 0x8000000c, 0x80000001); - nv_wait(priv, 0x616618 + hoff, 0x80000000, 0x00000000); + nv_mask(disp, 0x616618 + hoff, 0x8000000c, 0x80000001); + nv_wait(disp, 0x616618 + hoff, 0x80000000, 0x00000000); } - nv_mask(priv, 0x616548 + hoff, 0x00000070, 0x00000000); + nv_mask(disp, 0x616548 + hoff, 0x00000070, 0x00000000); for (i = 0; i < size; i++) - nv_wr32(priv, 0x10ec00 + soff, (i << 8) | args->v0.data[i]); + nv_wr32(disp, 0x10ec00 + soff, (i << 8) | args->v0.data[i]); for (; i < 0x60; i++) - nv_wr32(priv, 0x10ec00 + soff, (i << 8)); - nv_mask(priv, 0x10ec10 + soff, 0x80000003, 0x80000003); + nv_wr32(disp, 0x10ec00 + soff, (i << 8)); + nv_mask(disp, 0x10ec10 + soff, 0x80000003, 0x80000003); } else { if (outp->info.type == DCB_OUTPUT_DP) { - nv_mask(priv, 0x616618 + hoff, 0x80000001, 0x80000000); - nv_wait(priv, 0x616618 + hoff, 0x80000000, 0x00000000); + nv_mask(disp, 0x616618 + hoff, 0x80000001, 0x80000000); + nv_wait(disp, 0x616618 + hoff, 0x80000000, 0x00000000); } - nv_mask(priv, 0x10ec10 + soff, 0x80000003, 0x80000000 | !!size); + nv_mask(disp, 0x10ec10 + soff, 0x80000003, 0x80000000 | !!size); } return 0; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagt215.c index 891d1e7bf7d2..67d3cf99e0b5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagt215.c @@ -49,20 +49,20 @@ gt215_hda_eld(NV50_DISP_MTHD_V1) if (size && args->v0.data[0]) { if (outp->info.type == DCB_OUTPUT_DP) { - nv_mask(priv, 0x61c1e0 + soff, 0x8000000d, 0x80000001); - nv_wait(priv, 0x61c1e0 + soff, 0x80000000, 0x00000000); + nv_mask(disp, 0x61c1e0 + soff, 0x8000000d, 0x80000001); + nv_wait(disp, 0x61c1e0 + soff, 0x80000000, 0x00000000); } for (i = 0; i < size; i++) - nv_wr32(priv, 0x61c440 + soff, (i << 8) | args->v0.data[0]); + nv_wr32(disp, 0x61c440 + soff, (i << 8) | args->v0.data[0]); for (; i < 0x60; i++) - nv_wr32(priv, 0x61c440 + soff, (i << 8)); - nv_mask(priv, 0x61c448 + soff, 0x80000003, 0x80000003); + nv_wr32(disp, 0x61c440 + soff, (i << 8)); + nv_mask(disp, 0x61c448 + soff, 0x80000003, 0x80000003); } else { if (outp->info.type == DCB_OUTPUT_DP) { - nv_mask(priv, 0x61c1e0 + soff, 0x80000001, 0x80000000); - nv_wait(priv, 0x61c1e0 + soff, 0x80000000, 0x00000000); + nv_mask(disp, 0x61c1e0 + soff, 0x80000001, 0x80000000); + nv_wait(disp, 0x61c1e0 + soff, 0x80000000, 0x00000000); } - nv_mask(priv, 0x61c448 + soff, 0x80000003, 0x80000000 | !!size); + nv_mask(disp, 0x61c448 + soff, 0x80000003, 0x80000000 | !!size); } return 0; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmig84.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmig84.c index 621cb0b7ff19..0c282a4d31a8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmig84.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmig84.c @@ -54,38 +54,38 @@ g84_hdmi_ctrl(NV50_DISP_MTHD_V1) return ret; if (!(ctrl & 0x40000000)) { - nv_mask(priv, 0x6165a4 + hoff, 0x40000000, 0x00000000); - nv_mask(priv, 0x616520 + hoff, 0x00000001, 0x00000000); - nv_mask(priv, 0x616500 + hoff, 0x00000001, 0x00000000); + nv_mask(disp, 0x6165a4 + hoff, 0x40000000, 0x00000000); + nv_mask(disp, 0x616520 + hoff, 0x00000001, 0x00000000); + nv_mask(disp, 0x616500 + hoff, 0x00000001, 0x00000000); return 0; } /* AVI InfoFrame */ - nv_mask(priv, 0x616520 + hoff, 0x00000001, 0x00000000); - nv_wr32(priv, 0x616528 + hoff, 0x000d0282); - nv_wr32(priv, 0x61652c + hoff, 0x0000006f); - nv_wr32(priv, 0x616530 + hoff, 0x00000000); - nv_wr32(priv, 0x616534 + hoff, 0x00000000); - nv_wr32(priv, 0x616538 + hoff, 0x00000000); - nv_mask(priv, 0x616520 + hoff, 0x00000001, 0x00000001); + nv_mask(disp, 0x616520 + hoff, 0x00000001, 0x00000000); + nv_wr32(disp, 0x616528 + hoff, 0x000d0282); + nv_wr32(disp, 0x61652c + hoff, 0x0000006f); + nv_wr32(disp, 0x616530 + hoff, 0x00000000); + nv_wr32(disp, 0x616534 + hoff, 0x00000000); + nv_wr32(disp, 0x616538 + hoff, 0x00000000); + nv_mask(disp, 0x616520 + hoff, 0x00000001, 0x00000001); /* Audio InfoFrame */ - nv_mask(priv, 0x616500 + hoff, 0x00000001, 0x00000000); - nv_wr32(priv, 0x616508 + hoff, 0x000a0184); - nv_wr32(priv, 0x61650c + hoff, 0x00000071); - nv_wr32(priv, 0x616510 + hoff, 0x00000000); - nv_mask(priv, 0x616500 + hoff, 0x00000001, 0x00000001); + nv_mask(disp, 0x616500 + hoff, 0x00000001, 0x00000000); + nv_wr32(disp, 0x616508 + hoff, 0x000a0184); + nv_wr32(disp, 0x61650c + hoff, 0x00000071); + nv_wr32(disp, 0x616510 + hoff, 0x00000000); + nv_mask(disp, 0x616500 + hoff, 0x00000001, 0x00000001); - nv_mask(priv, 0x6165d0 + hoff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */ - nv_mask(priv, 0x616568 + hoff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */ - nv_mask(priv, 0x616578 + hoff, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */ + nv_mask(disp, 0x6165d0 + hoff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */ + nv_mask(disp, 0x616568 + hoff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */ + nv_mask(disp, 0x616578 + hoff, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */ /* ??? */ - nv_mask(priv, 0x61733c, 0x00100000, 0x00100000); /* RESETF */ - nv_mask(priv, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */ - nv_mask(priv, 0x61733c, 0x00100000, 0x00000000); /* !RESETF */ + nv_mask(disp, 0x61733c, 0x00100000, 0x00100000); /* RESETF */ + nv_mask(disp, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */ + nv_mask(disp, 0x61733c, 0x00100000, 0x00000000); /* !RESETF */ /* HDMI_CTRL */ - nv_mask(priv, 0x6165a4 + hoff, 0x5f1f007f, ctrl); + nv_mask(disp, 0x6165a4 + hoff, 0x5f1f007f, ctrl); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigf110.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigf110.c index c28449061bbd..5dcbc8e50d81 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigf110.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigf110.c @@ -53,27 +53,27 @@ gf110_hdmi_ctrl(NV50_DISP_MTHD_V1) return ret; if (!(ctrl & 0x40000000)) { - nv_mask(priv, 0x616798 + hoff, 0x40000000, 0x00000000); - nv_mask(priv, 0x6167a4 + hoff, 0x00000001, 0x00000000); - nv_mask(priv, 0x616714 + hoff, 0x00000001, 0x00000000); + nv_mask(disp, 0x616798 + hoff, 0x40000000, 0x00000000); + nv_mask(disp, 0x6167a4 + hoff, 0x00000001, 0x00000000); + nv_mask(disp, 0x616714 + hoff, 0x00000001, 0x00000000); return 0; } /* AVI InfoFrame */ - nv_mask(priv, 0x616714 + hoff, 0x00000001, 0x00000000); - nv_wr32(priv, 0x61671c + hoff, 0x000d0282); - nv_wr32(priv, 0x616720 + hoff, 0x0000006f); - nv_wr32(priv, 0x616724 + hoff, 0x00000000); - nv_wr32(priv, 0x616728 + hoff, 0x00000000); - nv_wr32(priv, 0x61672c + hoff, 0x00000000); - nv_mask(priv, 0x616714 + hoff, 0x00000001, 0x00000001); + nv_mask(disp, 0x616714 + hoff, 0x00000001, 0x00000000); + nv_wr32(disp, 0x61671c + hoff, 0x000d0282); + nv_wr32(disp, 0x616720 + hoff, 0x0000006f); + nv_wr32(disp, 0x616724 + hoff, 0x00000000); + nv_wr32(disp, 0x616728 + hoff, 0x00000000); + nv_wr32(disp, 0x61672c + hoff, 0x00000000); + nv_mask(disp, 0x616714 + hoff, 0x00000001, 0x00000001); /* ??? InfoFrame? */ - nv_mask(priv, 0x6167a4 + hoff, 0x00000001, 0x00000000); - nv_wr32(priv, 0x6167ac + hoff, 0x00000010); - nv_mask(priv, 0x6167a4 + hoff, 0x00000001, 0x00000001); + nv_mask(disp, 0x6167a4 + hoff, 0x00000001, 0x00000000); + nv_wr32(disp, 0x6167ac + hoff, 0x00000010); + nv_mask(disp, 0x6167a4 + hoff, 0x00000001, 0x00000001); /* HDMI_CTRL */ - nv_mask(priv, 0x616798 + hoff, 0x401f007f, ctrl); + nv_mask(disp, 0x616798 + hoff, 0x401f007f, ctrl); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigk104.c index ca34ff81ad7f..719d21e85301 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigk104.c @@ -54,30 +54,30 @@ gk104_hdmi_ctrl(NV50_DISP_MTHD_V1) return ret; if (!(ctrl & 0x40000000)) { - nv_mask(priv, 0x616798 + hoff, 0x40000000, 0x00000000); - nv_mask(priv, 0x6900c0 + hdmi, 0x00000001, 0x00000000); - nv_mask(priv, 0x690000 + hdmi, 0x00000001, 0x00000000); + nv_mask(disp, 0x616798 + hoff, 0x40000000, 0x00000000); + nv_mask(disp, 0x6900c0 + hdmi, 0x00000001, 0x00000000); + nv_mask(disp, 0x690000 + hdmi, 0x00000001, 0x00000000); return 0; } /* AVI InfoFrame */ - nv_mask(priv, 0x690000 + hdmi, 0x00000001, 0x00000000); - nv_wr32(priv, 0x690008 + hdmi, 0x000d0282); - nv_wr32(priv, 0x69000c + hdmi, 0x0000006f); - nv_wr32(priv, 0x690010 + hdmi, 0x00000000); - nv_wr32(priv, 0x690014 + hdmi, 0x00000000); - nv_wr32(priv, 0x690018 + hdmi, 0x00000000); - nv_mask(priv, 0x690000 + hdmi, 0x00000001, 0x00000001); + nv_mask(disp, 0x690000 + hdmi, 0x00000001, 0x00000000); + nv_wr32(disp, 0x690008 + hdmi, 0x000d0282); + nv_wr32(disp, 0x69000c + hdmi, 0x0000006f); + nv_wr32(disp, 0x690010 + hdmi, 0x00000000); + nv_wr32(disp, 0x690014 + hdmi, 0x00000000); + nv_wr32(disp, 0x690018 + hdmi, 0x00000000); + nv_mask(disp, 0x690000 + hdmi, 0x00000001, 0x00000001); /* ??? InfoFrame? */ - nv_mask(priv, 0x6900c0 + hdmi, 0x00000001, 0x00000000); - nv_wr32(priv, 0x6900cc + hdmi, 0x00000010); - nv_mask(priv, 0x6900c0 + hdmi, 0x00000001, 0x00000001); + nv_mask(disp, 0x6900c0 + hdmi, 0x00000001, 0x00000000); + nv_wr32(disp, 0x6900cc + hdmi, 0x00000010); + nv_mask(disp, 0x6900c0 + hdmi, 0x00000001, 0x00000001); /* ??? */ - nv_wr32(priv, 0x690080 + hdmi, 0x82000000); + nv_wr32(disp, 0x690080 + hdmi, 0x82000000); /* HDMI_CTRL */ - nv_mask(priv, 0x616798 + hoff, 0x401f007f, ctrl); + nv_mask(disp, 0x616798 + hoff, 0x401f007f, ctrl); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigt215.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigt215.c index b641c167dcfa..dde989158153 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigt215.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigt215.c @@ -55,38 +55,38 @@ gt215_hdmi_ctrl(NV50_DISP_MTHD_V1) return ret; if (!(ctrl & 0x40000000)) { - nv_mask(priv, 0x61c5a4 + soff, 0x40000000, 0x00000000); - nv_mask(priv, 0x61c520 + soff, 0x00000001, 0x00000000); - nv_mask(priv, 0x61c500 + soff, 0x00000001, 0x00000000); + nv_mask(disp, 0x61c5a4 + soff, 0x40000000, 0x00000000); + nv_mask(disp, 0x61c520 + soff, 0x00000001, 0x00000000); + nv_mask(disp, 0x61c500 + soff, 0x00000001, 0x00000000); return 0; } /* AVI InfoFrame */ - nv_mask(priv, 0x61c520 + soff, 0x00000001, 0x00000000); - nv_wr32(priv, 0x61c528 + soff, 0x000d0282); - nv_wr32(priv, 0x61c52c + soff, 0x0000006f); - nv_wr32(priv, 0x61c530 + soff, 0x00000000); - nv_wr32(priv, 0x61c534 + soff, 0x00000000); - nv_wr32(priv, 0x61c538 + soff, 0x00000000); - nv_mask(priv, 0x61c520 + soff, 0x00000001, 0x00000001); + nv_mask(disp, 0x61c520 + soff, 0x00000001, 0x00000000); + nv_wr32(disp, 0x61c528 + soff, 0x000d0282); + nv_wr32(disp, 0x61c52c + soff, 0x0000006f); + nv_wr32(disp, 0x61c530 + soff, 0x00000000); + nv_wr32(disp, 0x61c534 + soff, 0x00000000); + nv_wr32(disp, 0x61c538 + soff, 0x00000000); + nv_mask(disp, 0x61c520 + soff, 0x00000001, 0x00000001); /* Audio InfoFrame */ - nv_mask(priv, 0x61c500 + soff, 0x00000001, 0x00000000); - nv_wr32(priv, 0x61c508 + soff, 0x000a0184); - nv_wr32(priv, 0x61c50c + soff, 0x00000071); - nv_wr32(priv, 0x61c510 + soff, 0x00000000); - nv_mask(priv, 0x61c500 + soff, 0x00000001, 0x00000001); + nv_mask(disp, 0x61c500 + soff, 0x00000001, 0x00000000); + nv_wr32(disp, 0x61c508 + soff, 0x000a0184); + nv_wr32(disp, 0x61c50c + soff, 0x00000071); + nv_wr32(disp, 0x61c510 + soff, 0x00000000); + nv_mask(disp, 0x61c500 + soff, 0x00000001, 0x00000001); - nv_mask(priv, 0x61c5d0 + soff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */ - nv_mask(priv, 0x61c568 + soff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */ - nv_mask(priv, 0x61c578 + soff, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */ + nv_mask(disp, 0x61c5d0 + soff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */ + nv_mask(disp, 0x61c568 + soff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */ + nv_mask(disp, 0x61c578 + soff, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */ /* ??? */ - nv_mask(priv, 0x61733c, 0x00100000, 0x00100000); /* RESETF */ - nv_mask(priv, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */ - nv_mask(priv, 0x61733c, 0x00100000, 0x00000000); /* !RESETF */ + nv_mask(disp, 0x61733c, 0x00100000, 0x00100000); /* RESETF */ + nv_mask(disp, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */ + nv_mask(disp, 0x61733c, 0x00100000, 0x00000000); /* !RESETF */ /* HDMI_CTRL */ - nv_mask(priv, 0x61c5a4 + soff, 0x5f1f007f, ctrl); + nv_mask(disp, 0x61c5a4 + soff, 0x5f1f007f, ctrl); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c index b8f9e5c2b3c8..81359d25afce 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c @@ -28,12 +28,8 @@ #include #include -struct nv04_disp_priv { - struct nvkm_disp base; -}; - static int -nv04_disp_scanoutpos(struct nvkm_object *object, struct nv04_disp_priv *priv, +nv04_disp_scanoutpos(struct nvkm_object *object, struct nvkm_disp *disp, void *data, u32 size, int head) { const u32 hoff = head * 0x2000; @@ -46,12 +42,12 @@ nv04_disp_scanoutpos(struct nvkm_object *object, struct nv04_disp_priv *priv, nv_ioctl(object, "disp scanoutpos size %d\n", size); if (nvif_unpack(args->v0, 0, 0, false)) { nv_ioctl(object, "disp scanoutpos vers %d\n", args->v0.version); - args->v0.vblanks = nv_rd32(priv, 0x680800 + hoff) & 0xffff; - args->v0.vtotal = nv_rd32(priv, 0x680804 + hoff) & 0xffff; + args->v0.vblanks = nv_rd32(disp, 0x680800 + hoff) & 0xffff; + args->v0.vtotal = nv_rd32(disp, 0x680804 + hoff) & 0xffff; args->v0.vblanke = args->v0.vtotal - 1; - args->v0.hblanks = nv_rd32(priv, 0x680820 + hoff) & 0xffff; - args->v0.htotal = nv_rd32(priv, 0x680824 + hoff) & 0xffff; + args->v0.hblanks = nv_rd32(disp, 0x680820 + hoff) & 0xffff; + args->v0.htotal = nv_rd32(disp, 0x680824 + hoff) & 0xffff; args->v0.hblanke = args->v0.htotal - 1; /* @@ -63,7 +59,7 @@ nv04_disp_scanoutpos(struct nvkm_object *object, struct nv04_disp_priv *priv, return -ENOTSUPP; args->v0.time[0] = ktime_to_ns(ktime_get()); - line = nv_rd32(priv, 0x600868 + hoff); + line = nv_rd32(disp, 0x600868 + hoff); args->v0.time[1] = ktime_to_ns(ktime_get()); args->v0.hline = (line & 0xffff0000) >> 16; args->v0.vline = (line & 0x0000ffff); @@ -79,7 +75,7 @@ nv04_disp_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) union { struct nv04_disp_mthd_v0 v0; } *args = data; - struct nv04_disp_priv *priv = (void *)object->engine; + struct nvkm_disp *disp = (void *)object->engine; int head, ret; nv_ioctl(object, "disp mthd size %d\n", size); @@ -96,7 +92,7 @@ nv04_disp_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) switch (mthd) { case NV04_DISP_SCANOUTPOS: - return nv04_disp_scanoutpos(object, priv, data, size, head); + return nv04_disp_scanoutpos(object, disp, data, size, head); default: break; } @@ -148,27 +144,27 @@ nv04_disp_vblank_func = { static void nv04_disp_intr(struct nvkm_subdev *subdev) { - struct nv04_disp_priv *priv = (void *)subdev; - u32 crtc0 = nv_rd32(priv, 0x600100); - u32 crtc1 = nv_rd32(priv, 0x602100); + struct nvkm_disp *disp = (void *)subdev; + u32 crtc0 = nv_rd32(disp, 0x600100); + u32 crtc1 = nv_rd32(disp, 0x602100); u32 pvideo; if (crtc0 & 0x00000001) { - nvkm_disp_vblank(&priv->base, 0); - nv_wr32(priv, 0x600100, 0x00000001); + nvkm_disp_vblank(disp, 0); + nv_wr32(disp, 0x600100, 0x00000001); } if (crtc1 & 0x00000001) { - nvkm_disp_vblank(&priv->base, 1); - nv_wr32(priv, 0x602100, 0x00000001); + nvkm_disp_vblank(disp, 1); + nv_wr32(disp, 0x602100, 0x00000001); } - if (nv_device(priv)->chipset >= 0x10 && - nv_device(priv)->chipset <= 0x40) { - pvideo = nv_rd32(priv, 0x8100); + if (nv_device(disp)->chipset >= 0x10 && + nv_device(disp)->chipset <= 0x40) { + pvideo = nv_rd32(disp, 0x8100); if (pvideo & ~0x11) - nv_info(priv, "PVIDEO intr: %08x\n", pvideo); - nv_wr32(priv, 0x8100, pvideo); + nv_info(disp, "PVIDEO intr: %08x\n", pvideo); + nv_wr32(disp, 0x8100, pvideo); } } @@ -177,17 +173,17 @@ nv04_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nv04_disp_priv *priv; + struct nvkm_disp *disp; int ret; ret = nvkm_disp_create(parent, engine, oclass, 2, "DISPLAY", - "display", &priv); - *pobject = nv_object(priv); + "display", &disp); + *pobject = nv_object(disp); if (ret) return ret; - nv_engine(priv)->sclass = nv04_disp_sclass; - nv_subdev(priv)->intr = nv04_disp_intr; + nv_engine(disp)->sclass = nv04_disp_sclass; + nv_subdev(disp)->intr = nv04_disp_intr; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c index 25fcabcb1d6c..9551cfe5622a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c @@ -88,26 +88,26 @@ nv50_disp_chan_destroy(struct nv50_disp_chan *chan) static void nv50_disp_chan_uevent_fini(struct nvkm_event *event, int type, int index) { - struct nv50_disp_priv *priv = container_of(event, typeof(*priv), uevent); - nv_mask(priv, 0x610028, 0x00000001 << index, 0x00000000 << index); - nv_wr32(priv, 0x610020, 0x00000001 << index); + struct nv50_disp *disp = container_of(event, typeof(*disp), uevent); + nv_mask(disp, 0x610028, 0x00000001 << index, 0x00000000 << index); + nv_wr32(disp, 0x610020, 0x00000001 << index); } static void nv50_disp_chan_uevent_init(struct nvkm_event *event, int types, int index) { - struct nv50_disp_priv *priv = container_of(event, typeof(*priv), uevent); - nv_wr32(priv, 0x610020, 0x00000001 << index); - nv_mask(priv, 0x610028, 0x00000001 << index, 0x00000001 << index); + struct nv50_disp *disp = container_of(event, typeof(*disp), uevent); + nv_wr32(disp, 0x610020, 0x00000001 << index); + nv_mask(disp, 0x610028, 0x00000001 << index, 0x00000001 << index); } void -nv50_disp_chan_uevent_send(struct nv50_disp_priv *priv, int chid) +nv50_disp_chan_uevent_send(struct nv50_disp *disp, int chid) { struct nvif_notify_uevent_rep { } rep; - nvkm_event_send(&priv->uevent, 1, chid, &rep, sizeof(rep)); + nvkm_event_send(&disp->uevent, 1, chid, &rep, sizeof(rep)); } int @@ -141,10 +141,10 @@ int nv50_disp_chan_ntfy(struct nvkm_object *object, u32 type, struct nvkm_event **pevent) { - struct nv50_disp_priv *priv = (void *)object->engine; + struct nv50_disp *disp = (void *)object->engine; switch (type) { case NV50_DISP_CORE_CHANNEL_DMA_V0_NTFY_UEVENT: - *pevent = &priv->uevent; + *pevent = &disp->uevent; return 0; default: break; @@ -165,17 +165,17 @@ nv50_disp_chan_map(struct nvkm_object *object, u64 *addr, u32 *size) u32 nv50_disp_chan_rd32(struct nvkm_object *object, u64 addr) { - struct nv50_disp_priv *priv = (void *)object->engine; + struct nv50_disp *disp = (void *)object->engine; struct nv50_disp_chan *chan = (void *)object; - return nv_rd32(priv, 0x640000 + (chan->chid * 0x1000) + addr); + return nv_rd32(disp, 0x640000 + (chan->chid * 0x1000) + addr); } void nv50_disp_chan_wr32(struct nvkm_object *object, u64 addr, u32 data) { - struct nv50_disp_priv *priv = (void *)object->engine; + struct nv50_disp *disp = (void *)object->engine; struct nv50_disp_chan *chan = (void *)object; - nv_wr32(priv, 0x640000 + (chan->chid * 0x1000) + addr, data); + nv_wr32(disp, 0x640000 + (chan->chid * 0x1000) + addr, data); } /******************************************************************************* @@ -255,7 +255,7 @@ nv50_disp_dmac_dtor(struct nvkm_object *object) static int nv50_disp_dmac_init(struct nvkm_object *object) { - struct nv50_disp_priv *priv = (void *)object->engine; + struct nv50_disp *disp = (void *)object->engine; struct nv50_disp_dmac *dmac = (void *)object; int chid = dmac->base.chid; int ret; @@ -265,20 +265,20 @@ nv50_disp_dmac_init(struct nvkm_object *object) return ret; /* enable error reporting */ - nv_mask(priv, 0x610028, 0x00010000 << chid, 0x00010000 << chid); + nv_mask(disp, 0x610028, 0x00010000 << chid, 0x00010000 << chid); /* initialise channel for dma command submission */ - nv_wr32(priv, 0x610204 + (chid * 0x0010), dmac->push); - nv_wr32(priv, 0x610208 + (chid * 0x0010), 0x00010000); - nv_wr32(priv, 0x61020c + (chid * 0x0010), chid); - nv_mask(priv, 0x610200 + (chid * 0x0010), 0x00000010, 0x00000010); - nv_wr32(priv, 0x640000 + (chid * 0x1000), 0x00000000); - nv_wr32(priv, 0x610200 + (chid * 0x0010), 0x00000013); + nv_wr32(disp, 0x610204 + (chid * 0x0010), dmac->push); + nv_wr32(disp, 0x610208 + (chid * 0x0010), 0x00010000); + nv_wr32(disp, 0x61020c + (chid * 0x0010), chid); + nv_mask(disp, 0x610200 + (chid * 0x0010), 0x00000010, 0x00000010); + nv_wr32(disp, 0x640000 + (chid * 0x1000), 0x00000000); + nv_wr32(disp, 0x610200 + (chid * 0x0010), 0x00000013); /* wait for it to go inactive */ - if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x80000000, 0x00000000)) { + if (!nv_wait(disp, 0x610200 + (chid * 0x10), 0x80000000, 0x00000000)) { nv_error(dmac, "init timeout, 0x%08x\n", - nv_rd32(priv, 0x610200 + (chid * 0x10))); + nv_rd32(disp, 0x610200 + (chid * 0x10))); return -EBUSY; } @@ -288,22 +288,22 @@ nv50_disp_dmac_init(struct nvkm_object *object) static int nv50_disp_dmac_fini(struct nvkm_object *object, bool suspend) { - struct nv50_disp_priv *priv = (void *)object->engine; + struct nv50_disp *disp = (void *)object->engine; struct nv50_disp_dmac *dmac = (void *)object; int chid = dmac->base.chid; /* deactivate channel */ - nv_mask(priv, 0x610200 + (chid * 0x0010), 0x00001010, 0x00001000); - nv_mask(priv, 0x610200 + (chid * 0x0010), 0x00000003, 0x00000000); - if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x001e0000, 0x00000000)) { + nv_mask(disp, 0x610200 + (chid * 0x0010), 0x00001010, 0x00001000); + nv_mask(disp, 0x610200 + (chid * 0x0010), 0x00000003, 0x00000000); + if (!nv_wait(disp, 0x610200 + (chid * 0x10), 0x001e0000, 0x00000000)) { nv_error(dmac, "fini timeout, 0x%08x\n", - nv_rd32(priv, 0x610200 + (chid * 0x10))); + nv_rd32(disp, 0x610200 + (chid * 0x10))); if (suspend) return -EBUSY; } /* disable error reporting and completion notifications */ - nv_mask(priv, 0x610028, 0x00010001 << chid, 0x00000000 << chid); + nv_mask(disp, 0x610028, 0x00010001 << chid, 0x00000000 << chid); return nv50_disp_chan_fini(&dmac->base, suspend); } @@ -313,16 +313,16 @@ nv50_disp_dmac_fini(struct nvkm_object *object, bool suspend) ******************************************************************************/ static void -nv50_disp_mthd_list(struct nv50_disp_priv *priv, int debug, u32 base, int c, +nv50_disp_mthd_list(struct nv50_disp *disp, int debug, u32 base, int c, const struct nv50_disp_mthd_list *list, int inst) { - struct nvkm_object *disp = nv_object(priv); + struct nvkm_object *object = nv_object(disp); int i; for (i = 0; list->data[i].mthd; i++) { if (list->data[i].addr) { - u32 next = nv_rd32(priv, list->data[i].addr + base + 0); - u32 prev = nv_rd32(priv, list->data[i].addr + base + c); + u32 next = nv_rd32(disp, list->data[i].addr + base + 0); + u32 prev = nv_rd32(disp, list->data[i].addr + base + c); u32 mthd = list->data[i].mthd + (list->mthd * inst); const char *name = list->data[i].name; char mods[16]; @@ -332,7 +332,7 @@ nv50_disp_mthd_list(struct nv50_disp_priv *priv, int debug, u32 base, int c, else snprintf(mods, sizeof(mods), "%13c", ' '); - nv_printk_(disp, debug, "\t0x%04x: 0x%08x %s%s%s\n", + nv_printk_(object, debug, "\t0x%04x: 0x%08x %s%s%s\n", mthd, prev, mods, name ? " // " : "", name ? name : ""); } @@ -340,15 +340,15 @@ nv50_disp_mthd_list(struct nv50_disp_priv *priv, int debug, u32 base, int c, } void -nv50_disp_mthd_chan(struct nv50_disp_priv *priv, int debug, int head, +nv50_disp_mthd_chan(struct nv50_disp *disp, int debug, int head, const struct nv50_disp_mthd_chan *chan) { - struct nvkm_object *disp = nv_object(priv); - const struct nv50_disp_impl *impl = (void *)disp->oclass; + struct nvkm_object *object = nv_object(disp); + const struct nv50_disp_impl *impl = (void *)object->oclass; const struct nv50_disp_mthd_list *list; int i, j; - if (debug > nv_subdev(priv)->debug) + if (debug > nv_subdev(disp)->debug) return; for (i = 0; (list = chan->data[i].mthd) != NULL; i++) { @@ -370,8 +370,8 @@ nv50_disp_mthd_chan(struct nv50_disp_priv *priv, int debug, int head, sname = sname_; } - nv_printk_(disp, debug, "%s%s:\n", cname, sname); - nv50_disp_mthd_list(priv, debug, base, impl->mthd.prev, + nv_printk_(object, debug, "%s%s:\n", cname, sname); + nv50_disp_mthd_list(disp, debug, base, impl->mthd.prev, list, j); } } @@ -515,7 +515,7 @@ nv50_disp_core_ctor(struct nvkm_object *parent, static int nv50_disp_core_init(struct nvkm_object *object) { - struct nv50_disp_priv *priv = (void *)object->engine; + struct nv50_disp *disp = (void *)object->engine; struct nv50_disp_dmac *mast = (void *)object; int ret; @@ -524,25 +524,25 @@ nv50_disp_core_init(struct nvkm_object *object) return ret; /* enable error reporting */ - nv_mask(priv, 0x610028, 0x00010000, 0x00010000); + nv_mask(disp, 0x610028, 0x00010000, 0x00010000); /* attempt to unstick channel from some unknown state */ - if ((nv_rd32(priv, 0x610200) & 0x009f0000) == 0x00020000) - nv_mask(priv, 0x610200, 0x00800000, 0x00800000); - if ((nv_rd32(priv, 0x610200) & 0x003f0000) == 0x00030000) - nv_mask(priv, 0x610200, 0x00600000, 0x00600000); + if ((nv_rd32(disp, 0x610200) & 0x009f0000) == 0x00020000) + nv_mask(disp, 0x610200, 0x00800000, 0x00800000); + if ((nv_rd32(disp, 0x610200) & 0x003f0000) == 0x00030000) + nv_mask(disp, 0x610200, 0x00600000, 0x00600000); /* initialise channel for dma command submission */ - nv_wr32(priv, 0x610204, mast->push); - nv_wr32(priv, 0x610208, 0x00010000); - nv_wr32(priv, 0x61020c, 0x00000000); - nv_mask(priv, 0x610200, 0x00000010, 0x00000010); - nv_wr32(priv, 0x640000, 0x00000000); - nv_wr32(priv, 0x610200, 0x01000013); + nv_wr32(disp, 0x610204, mast->push); + nv_wr32(disp, 0x610208, 0x00010000); + nv_wr32(disp, 0x61020c, 0x00000000); + nv_mask(disp, 0x610200, 0x00000010, 0x00000010); + nv_wr32(disp, 0x640000, 0x00000000); + nv_wr32(disp, 0x610200, 0x01000013); /* wait for it to go inactive */ - if (!nv_wait(priv, 0x610200, 0x80000000, 0x00000000)) { - nv_error(mast, "init: 0x%08x\n", nv_rd32(priv, 0x610200)); + if (!nv_wait(disp, 0x610200, 0x80000000, 0x00000000)) { + nv_error(mast, "init: 0x%08x\n", nv_rd32(disp, 0x610200)); return -EBUSY; } @@ -552,20 +552,20 @@ nv50_disp_core_init(struct nvkm_object *object) static int nv50_disp_core_fini(struct nvkm_object *object, bool suspend) { - struct nv50_disp_priv *priv = (void *)object->engine; + struct nv50_disp *disp = (void *)object->engine; struct nv50_disp_dmac *mast = (void *)object; /* deactivate channel */ - nv_mask(priv, 0x610200, 0x00000010, 0x00000000); - nv_mask(priv, 0x610200, 0x00000003, 0x00000000); - if (!nv_wait(priv, 0x610200, 0x001e0000, 0x00000000)) { - nv_error(mast, "fini: 0x%08x\n", nv_rd32(priv, 0x610200)); + nv_mask(disp, 0x610200, 0x00000010, 0x00000000); + nv_mask(disp, 0x610200, 0x00000003, 0x00000000); + if (!nv_wait(disp, 0x610200, 0x001e0000, 0x00000000)) { + nv_error(mast, "fini: 0x%08x\n", nv_rd32(disp, 0x610200)); if (suspend) return -EBUSY; } /* disable error reporting and completion notifications */ - nv_mask(priv, 0x610028, 0x00010001, 0x00000000); + nv_mask(disp, 0x610028, 0x00010001, 0x00000000); return nv50_disp_chan_fini(&mast->base, suspend); } @@ -648,7 +648,7 @@ nv50_disp_base_ctor(struct nvkm_object *parent, union { struct nv50_disp_base_channel_dma_v0 v0; } *args = data; - struct nv50_disp_priv *priv = (void *)engine; + struct nv50_disp *disp = (void *)engine; struct nv50_disp_dmac *dmac; int ret; @@ -657,7 +657,7 @@ nv50_disp_base_ctor(struct nvkm_object *parent, nv_ioctl(parent, "create disp base channel dma vers %d " "pushbuf %08x head %d\n", args->v0.version, args->v0.pushbuf, args->v0.head); - if (args->v0.head > priv->head.nr) + if (args->v0.head > disp->head.nr) return -EINVAL; } else return ret; @@ -738,7 +738,7 @@ nv50_disp_ovly_ctor(struct nvkm_object *parent, union { struct nv50_disp_overlay_channel_dma_v0 v0; } *args = data; - struct nv50_disp_priv *priv = (void *)engine; + struct nv50_disp *disp = (void *)engine; struct nv50_disp_dmac *dmac; int ret; @@ -747,7 +747,7 @@ nv50_disp_ovly_ctor(struct nvkm_object *parent, nv_ioctl(parent, "create disp overlay channel dma vers %d " "pushbuf %08x head %d\n", args->v0.version, args->v0.pushbuf, args->v0.head); - if (args->v0.head > priv->head.nr) + if (args->v0.head > disp->head.nr) return -EINVAL; } else return ret; @@ -801,7 +801,7 @@ nv50_disp_pioc_dtor(struct nvkm_object *object) static int nv50_disp_pioc_init(struct nvkm_object *object) { - struct nv50_disp_priv *priv = (void *)object->engine; + struct nv50_disp *disp = (void *)object->engine; struct nv50_disp_pioc *pioc = (void *)object; int chid = pioc->base.chid; int ret; @@ -810,17 +810,17 @@ nv50_disp_pioc_init(struct nvkm_object *object) if (ret) return ret; - nv_wr32(priv, 0x610200 + (chid * 0x10), 0x00002000); - if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x00000000, 0x00000000)) { + nv_wr32(disp, 0x610200 + (chid * 0x10), 0x00002000); + if (!nv_wait(disp, 0x610200 + (chid * 0x10), 0x00000000, 0x00000000)) { nv_error(pioc, "timeout0: 0x%08x\n", - nv_rd32(priv, 0x610200 + (chid * 0x10))); + nv_rd32(disp, 0x610200 + (chid * 0x10))); return -EBUSY; } - nv_wr32(priv, 0x610200 + (chid * 0x10), 0x00000001); - if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x00030000, 0x00010000)) { + nv_wr32(disp, 0x610200 + (chid * 0x10), 0x00000001); + if (!nv_wait(disp, 0x610200 + (chid * 0x10), 0x00030000, 0x00010000)) { nv_error(pioc, "timeout1: 0x%08x\n", - nv_rd32(priv, 0x610200 + (chid * 0x10))); + nv_rd32(disp, 0x610200 + (chid * 0x10))); return -EBUSY; } @@ -830,14 +830,14 @@ nv50_disp_pioc_init(struct nvkm_object *object) static int nv50_disp_pioc_fini(struct nvkm_object *object, bool suspend) { - struct nv50_disp_priv *priv = (void *)object->engine; + struct nv50_disp *disp = (void *)object->engine; struct nv50_disp_pioc *pioc = (void *)object; int chid = pioc->base.chid; - nv_mask(priv, 0x610200 + (chid * 0x10), 0x00000001, 0x00000000); - if (!nv_wait(priv, 0x610200 + (chid * 0x10), 0x00030000, 0x00000000)) { + nv_mask(disp, 0x610200 + (chid * 0x10), 0x00000001, 0x00000000); + if (!nv_wait(disp, 0x610200 + (chid * 0x10), 0x00030000, 0x00000000)) { nv_error(pioc, "timeout: 0x%08x\n", - nv_rd32(priv, 0x610200 + (chid * 0x10))); + nv_rd32(disp, 0x610200 + (chid * 0x10))); if (suspend) return -EBUSY; } @@ -858,7 +858,7 @@ nv50_disp_oimm_ctor(struct nvkm_object *parent, union { struct nv50_disp_overlay_v0 v0; } *args = data; - struct nv50_disp_priv *priv = (void *)engine; + struct nv50_disp *disp = (void *)engine; struct nv50_disp_pioc *pioc; int ret; @@ -866,7 +866,7 @@ nv50_disp_oimm_ctor(struct nvkm_object *parent, if (nvif_unpack(args->v0, 0, 0, false)) { nv_ioctl(parent, "create disp overlay vers %d head %d\n", args->v0.version, args->v0.head); - if (args->v0.head > priv->head.nr) + if (args->v0.head > disp->head.nr) return -EINVAL; } else return ret; @@ -906,7 +906,7 @@ nv50_disp_curs_ctor(struct nvkm_object *parent, union { struct nv50_disp_cursor_v0 v0; } *args = data; - struct nv50_disp_priv *priv = (void *)engine; + struct nv50_disp *disp = (void *)engine; struct nv50_disp_pioc *pioc; int ret; @@ -914,7 +914,7 @@ nv50_disp_curs_ctor(struct nvkm_object *parent, if (nvif_unpack(args->v0, 0, 0, false)) { nv_ioctl(parent, "create disp cursor vers %d head %d\n", args->v0.version, args->v0.head); - if (args->v0.head > priv->head.nr) + if (args->v0.head > disp->head.nr) return -EINVAL; } else return ret; @@ -948,9 +948,9 @@ nv50_disp_curs_ofuncs = { int nv50_disp_main_scanoutpos(NV50_DISP_MTHD_V0) { - const u32 blanke = nv_rd32(priv, 0x610aec + (head * 0x540)); - const u32 blanks = nv_rd32(priv, 0x610af4 + (head * 0x540)); - const u32 total = nv_rd32(priv, 0x610afc + (head * 0x540)); + const u32 blanke = nv_rd32(disp, 0x610aec + (head * 0x540)); + const u32 blanks = nv_rd32(disp, 0x610af4 + (head * 0x540)); + const u32 total = nv_rd32(disp, 0x610afc + (head * 0x540)); union { struct nv04_disp_scanoutpos_v0 v0; } *args = data; @@ -967,10 +967,10 @@ nv50_disp_main_scanoutpos(NV50_DISP_MTHD_V0) args->v0.htotal = ( total & 0x0000ffff); args->v0.time[0] = ktime_to_ns(ktime_get()); args->v0.vline = /* vline read locks hline */ - nv_rd32(priv, 0x616340 + (head * 0x800)) & 0xffff; + nv_rd32(disp, 0x616340 + (head * 0x800)) & 0xffff; args->v0.time[1] = ktime_to_ns(ktime_get()); args->v0.hline = - nv_rd32(priv, 0x616344 + (head * 0x800)) & 0xffff; + nv_rd32(disp, 0x616344 + (head * 0x800)) & 0xffff; } else return ret; @@ -985,7 +985,7 @@ nv50_disp_main_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) struct nv50_disp_mthd_v0 v0; struct nv50_disp_mthd_v1 v1; } *args = data; - struct nv50_disp_priv *priv = (void *)object->engine; + struct nv50_disp *disp = (void *)object->engine; struct nvkm_output *outp = NULL; struct nvkm_output *temp; u16 type, mask = 0; @@ -1013,11 +1013,11 @@ nv50_disp_main_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) } else return ret; - if (head < 0 || head >= priv->head.nr) + if (head < 0 || head >= disp->head.nr) return -ENXIO; if (mask) { - list_for_each_entry(temp, &priv->base.outp, head) { + list_for_each_entry(temp, &disp->base.outp, head) { if ((temp->info.hasht == type) && (temp->info.hashm & mask) == mask) { outp = temp; @@ -1030,26 +1030,26 @@ nv50_disp_main_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) switch (mthd) { case NV50_DISP_SCANOUTPOS: - return impl->head.scanoutpos(object, priv, data, size, head); + return impl->head.scanoutpos(object, disp, data, size, head); default: break; } switch (mthd * !!outp) { case NV50_DISP_MTHD_V1_DAC_PWR: - return priv->dac.power(object, priv, data, size, head, outp); + return disp->dac.power(object, disp, data, size, head, outp); case NV50_DISP_MTHD_V1_DAC_LOAD: - return priv->dac.sense(object, priv, data, size, head, outp); + return disp->dac.sense(object, disp, data, size, head, outp); case NV50_DISP_MTHD_V1_SOR_PWR: - return priv->sor.power(object, priv, data, size, head, outp); + return disp->sor.power(object, disp, data, size, head, outp); case NV50_DISP_MTHD_V1_SOR_HDA_ELD: - if (!priv->sor.hda_eld) + if (!disp->sor.hda_eld) return -ENODEV; - return priv->sor.hda_eld(object, priv, data, size, head, outp); + return disp->sor.hda_eld(object, disp, data, size, head, outp); case NV50_DISP_MTHD_V1_SOR_HDMI_PWR: - if (!priv->sor.hdmi) + if (!disp->sor.hdmi) return -ENODEV; - return priv->sor.hdmi(object, priv, data, size, head, outp); + return disp->sor.hdmi(object, disp, data, size, head, outp); case NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT: { union { struct nv50_disp_sor_lvds_script_v0 v0; @@ -1059,7 +1059,7 @@ nv50_disp_main_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) nv_ioctl(object, "disp sor lvds script " "vers %d name %04x\n", args->v0.version, args->v0.script); - priv->sor.lvdsconf = args->v0.script; + disp->sor.lvdsconf = args->v0.script; return 0; } else return ret; @@ -1090,9 +1090,9 @@ nv50_disp_main_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size) } break; case NV50_DISP_MTHD_V1_PIOR_PWR: - if (!priv->pior.power) + if (!disp->pior.power) return -ENODEV; - return priv->pior.power(object, priv, data, size, head, outp); + return disp->pior.power(object, disp, data, size, head, outp); default: break; } @@ -1106,12 +1106,12 @@ nv50_disp_main_ctor(struct nvkm_object *parent, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nv50_disp_priv *priv = (void *)engine; + struct nv50_disp *disp = (void *)engine; struct nv50_disp_base *base; int ret; ret = nvkm_parent_create(parent, engine, oclass, 0, - priv->sclass, 0, &base); + disp->sclass, 0, &base); *pobject = nv_object(base); if (ret) return ret; @@ -1131,7 +1131,7 @@ nv50_disp_main_dtor(struct nvkm_object *object) static int nv50_disp_main_init(struct nvkm_object *object) { - struct nv50_disp_priv *priv = (void *)object->engine; + struct nv50_disp *disp = (void *)object->engine; struct nv50_disp_base *base = (void *)object; int ret, i; u32 tmp; @@ -1144,67 +1144,67 @@ nv50_disp_main_init(struct nvkm_object *object) * another appear to inform EVO of the display capabilities or * something similar. NFI what the 0x614004 caps are for.. */ - tmp = nv_rd32(priv, 0x614004); - nv_wr32(priv, 0x610184, tmp); + tmp = nv_rd32(disp, 0x614004); + nv_wr32(disp, 0x610184, tmp); /* ... CRTC caps */ - for (i = 0; i < priv->head.nr; i++) { - tmp = nv_rd32(priv, 0x616100 + (i * 0x800)); - nv_wr32(priv, 0x610190 + (i * 0x10), tmp); - tmp = nv_rd32(priv, 0x616104 + (i * 0x800)); - nv_wr32(priv, 0x610194 + (i * 0x10), tmp); - tmp = nv_rd32(priv, 0x616108 + (i * 0x800)); - nv_wr32(priv, 0x610198 + (i * 0x10), tmp); - tmp = nv_rd32(priv, 0x61610c + (i * 0x800)); - nv_wr32(priv, 0x61019c + (i * 0x10), tmp); + for (i = 0; i < disp->head.nr; i++) { + tmp = nv_rd32(disp, 0x616100 + (i * 0x800)); + nv_wr32(disp, 0x610190 + (i * 0x10), tmp); + tmp = nv_rd32(disp, 0x616104 + (i * 0x800)); + nv_wr32(disp, 0x610194 + (i * 0x10), tmp); + tmp = nv_rd32(disp, 0x616108 + (i * 0x800)); + nv_wr32(disp, 0x610198 + (i * 0x10), tmp); + tmp = nv_rd32(disp, 0x61610c + (i * 0x800)); + nv_wr32(disp, 0x61019c + (i * 0x10), tmp); } /* ... DAC caps */ - for (i = 0; i < priv->dac.nr; i++) { - tmp = nv_rd32(priv, 0x61a000 + (i * 0x800)); - nv_wr32(priv, 0x6101d0 + (i * 0x04), tmp); + for (i = 0; i < disp->dac.nr; i++) { + tmp = nv_rd32(disp, 0x61a000 + (i * 0x800)); + nv_wr32(disp, 0x6101d0 + (i * 0x04), tmp); } /* ... SOR caps */ - for (i = 0; i < priv->sor.nr; i++) { - tmp = nv_rd32(priv, 0x61c000 + (i * 0x800)); - nv_wr32(priv, 0x6101e0 + (i * 0x04), tmp); + for (i = 0; i < disp->sor.nr; i++) { + tmp = nv_rd32(disp, 0x61c000 + (i * 0x800)); + nv_wr32(disp, 0x6101e0 + (i * 0x04), tmp); } /* ... PIOR caps */ - for (i = 0; i < priv->pior.nr; i++) { - tmp = nv_rd32(priv, 0x61e000 + (i * 0x800)); - nv_wr32(priv, 0x6101f0 + (i * 0x04), tmp); + for (i = 0; i < disp->pior.nr; i++) { + tmp = nv_rd32(disp, 0x61e000 + (i * 0x800)); + nv_wr32(disp, 0x6101f0 + (i * 0x04), tmp); } /* steal display away from vbios, or something like that */ - if (nv_rd32(priv, 0x610024) & 0x00000100) { - nv_wr32(priv, 0x610024, 0x00000100); - nv_mask(priv, 0x6194e8, 0x00000001, 0x00000000); - if (!nv_wait(priv, 0x6194e8, 0x00000002, 0x00000000)) { - nv_error(priv, "timeout acquiring display\n"); + if (nv_rd32(disp, 0x610024) & 0x00000100) { + nv_wr32(disp, 0x610024, 0x00000100); + nv_mask(disp, 0x6194e8, 0x00000001, 0x00000000); + if (!nv_wait(disp, 0x6194e8, 0x00000002, 0x00000000)) { + nv_error(disp, "timeout acquiring display\n"); return -EBUSY; } } /* point at display engine memory area (hash table, objects) */ - nv_wr32(priv, 0x610010, (nv_gpuobj(base->ramht)->addr >> 8) | 9); + nv_wr32(disp, 0x610010, (nv_gpuobj(base->ramht)->addr >> 8) | 9); /* enable supervisor interrupts, disable everything else */ - nv_wr32(priv, 0x61002c, 0x00000370); - nv_wr32(priv, 0x610028, 0x00000000); + nv_wr32(disp, 0x61002c, 0x00000370); + nv_wr32(disp, 0x610028, 0x00000000); return 0; } static int nv50_disp_main_fini(struct nvkm_object *object, bool suspend) { - struct nv50_disp_priv *priv = (void *)object->engine; + struct nv50_disp *disp = (void *)object->engine; struct nv50_disp_base *base = (void *)object; /* disable all interrupts */ - nv_wr32(priv, 0x610024, 0x00000000); - nv_wr32(priv, 0x610020, 0x00000000); + nv_wr32(disp, 0x610024, 0x00000000); + nv_wr32(disp, 0x610020, 0x00000000); return nvkm_parent_fini(&base->base, suspend); } @@ -1246,7 +1246,7 @@ nv50_disp_data_ctor(struct nvkm_object *parent, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nv50_disp_priv *priv = (void *)engine; + struct nv50_disp *disp = (void *)engine; struct nvkm_engctx *ectx; int ret = -EBUSY; @@ -1258,13 +1258,13 @@ nv50_disp_data_ctor(struct nvkm_object *parent, } /* allocate display hardware to client */ - mutex_lock(&nv_subdev(priv)->mutex); - if (list_empty(&nv_engine(priv)->contexts)) { + mutex_lock(&nv_subdev(disp)->mutex); + if (list_empty(&nv_engine(disp)->contexts)) { ret = nvkm_engctx_create(parent, engine, oclass, NULL, 0x10000, 0x10000, NVOBJ_FLAG_HEAP, &ectx); *pobject = nv_object(ectx); } - mutex_unlock(&nv_subdev(priv)->mutex); + mutex_unlock(&nv_subdev(disp)->mutex); return ret; } @@ -1322,11 +1322,11 @@ nv50_disp_intr_error_code[] = { }; static void -nv50_disp_intr_error(struct nv50_disp_priv *priv, int chid) +nv50_disp_intr_error(struct nv50_disp *disp, int chid) { - struct nv50_disp_impl *impl = (void *)nv_object(priv)->oclass; - u32 data = nv_rd32(priv, 0x610084 + (chid * 0x08)); - u32 addr = nv_rd32(priv, 0x610080 + (chid * 0x08)); + struct nv50_disp_impl *impl = (void *)nv_object(disp)->oclass; + u32 data = nv_rd32(disp, 0x610084 + (chid * 0x08)); + u32 addr = nv_rd32(disp, 0x610080 + (chid * 0x08)); u32 code = (addr & 0x00ff0000) >> 16; u32 type = (addr & 0x00007000) >> 12; u32 mthd = (addr & 0x00000ffc); @@ -1341,14 +1341,14 @@ nv50_disp_intr_error(struct nv50_disp_priv *priv, int chid) if (!ec) snprintf(ecunk, sizeof(ecunk), "UNK%02X", code); - nv_error(priv, "%s [%s] chid %d mthd 0x%04x data 0x%08x\n", + nv_error(disp, "%s [%s] chid %d mthd 0x%04x data 0x%08x\n", et ? et->name : etunk, ec ? ec->name : ecunk, chid, mthd, data); if (chid == 0) { switch (mthd) { case 0x0080: - nv50_disp_mthd_chan(priv, NV_DBG_ERROR, chid - 0, + nv50_disp_mthd_chan(disp, NV_DBG_ERROR, chid - 0, impl->mthd.core); break; default: @@ -1358,7 +1358,7 @@ nv50_disp_intr_error(struct nv50_disp_priv *priv, int chid) if (chid <= 2) { switch (mthd) { case 0x0080: - nv50_disp_mthd_chan(priv, NV_DBG_ERROR, chid - 1, + nv50_disp_mthd_chan(disp, NV_DBG_ERROR, chid - 1, impl->mthd.base); break; default: @@ -1368,7 +1368,7 @@ nv50_disp_intr_error(struct nv50_disp_priv *priv, int chid) if (chid <= 4) { switch (mthd) { case 0x0080: - nv50_disp_mthd_chan(priv, NV_DBG_ERROR, chid - 3, + nv50_disp_mthd_chan(disp, NV_DBG_ERROR, chid - 3, impl->mthd.ovly); break; default: @@ -1376,16 +1376,16 @@ nv50_disp_intr_error(struct nv50_disp_priv *priv, int chid) } } - nv_wr32(priv, 0x610020, 0x00010000 << chid); - nv_wr32(priv, 0x610080 + (chid * 0x08), 0x90000000); + nv_wr32(disp, 0x610020, 0x00010000 << chid); + nv_wr32(disp, 0x610080 + (chid * 0x08), 0x90000000); } static struct nvkm_output * -exec_lookup(struct nv50_disp_priv *priv, int head, int or, u32 ctrl, +exec_lookup(struct nv50_disp *disp, int head, int or, u32 ctrl, u32 *data, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_outp *info) { - struct nvkm_bios *bios = nvkm_bios(priv); + struct nvkm_bios *bios = nvkm_bios(disp); struct nvkm_output *outp; u16 mask, type; @@ -1402,7 +1402,7 @@ exec_lookup(struct nv50_disp_priv *priv, int head, int or, u32 ctrl, case 0x00000800: type = DCB_OUTPUT_DP; mask = 1; break; case 0x00000900: type = DCB_OUTPUT_DP; mask = 2; break; default: - nv_error(priv, "unknown SOR mc 0x%08x\n", ctrl); + nv_error(disp, "unknown SOR mc 0x%08x\n", ctrl); return NULL; } or -= 4; @@ -1411,9 +1411,9 @@ exec_lookup(struct nv50_disp_priv *priv, int head, int or, u32 ctrl, type = 0x0010; mask = 0; switch (ctrl & 0x00000f00) { - case 0x00000000: type |= priv->pior.type[or]; break; + case 0x00000000: type |= disp->pior.type[or]; break; default: - nv_error(priv, "unknown PIOR mc 0x%08x\n", ctrl); + nv_error(disp, "unknown PIOR mc 0x%08x\n", ctrl); return NULL; } } @@ -1422,7 +1422,7 @@ exec_lookup(struct nv50_disp_priv *priv, int head, int or, u32 ctrl, mask |= 0x0001 << or; mask |= 0x0100 << head; - list_for_each_entry(outp, &priv->base.outp, head) { + list_for_each_entry(outp, &disp->base.outp, head) { if ((outp->info.hasht & 0xff) == type && (outp->info.hashm & mask) == mask) { *data = nvbios_outp_match(bios, outp->info.hasht, @@ -1438,9 +1438,9 @@ exec_lookup(struct nv50_disp_priv *priv, int head, int or, u32 ctrl, } static struct nvkm_output * -exec_script(struct nv50_disp_priv *priv, int head, int id) +exec_script(struct nv50_disp *disp, int head, int id) { - struct nvkm_bios *bios = nvkm_bios(priv); + struct nvkm_bios *bios = nvkm_bios(disp); struct nvkm_output *outp; struct nvbios_outp info; u8 ver, hdr, cnt, len; @@ -1449,27 +1449,27 @@ exec_script(struct nv50_disp_priv *priv, int head, int id) int i; /* DAC */ - for (i = 0; !(ctrl & (1 << head)) && i < priv->dac.nr; i++) - ctrl = nv_rd32(priv, 0x610b5c + (i * 8)); + for (i = 0; !(ctrl & (1 << head)) && i < disp->dac.nr; i++) + ctrl = nv_rd32(disp, 0x610b5c + (i * 8)); /* SOR */ if (!(ctrl & (1 << head))) { - if (nv_device(priv)->chipset < 0x90 || - nv_device(priv)->chipset == 0x92 || - nv_device(priv)->chipset == 0xa0) { + if (nv_device(disp)->chipset < 0x90 || + nv_device(disp)->chipset == 0x92 || + nv_device(disp)->chipset == 0xa0) { reg = 0x610b74; } else { reg = 0x610798; } - for (i = 0; !(ctrl & (1 << head)) && i < priv->sor.nr; i++) - ctrl = nv_rd32(priv, reg + (i * 8)); + for (i = 0; !(ctrl & (1 << head)) && i < disp->sor.nr; i++) + ctrl = nv_rd32(disp, reg + (i * 8)); i += 4; } /* PIOR */ if (!(ctrl & (1 << head))) { - for (i = 0; !(ctrl & (1 << head)) && i < priv->pior.nr; i++) - ctrl = nv_rd32(priv, 0x610b84 + (i * 8)); + for (i = 0; !(ctrl & (1 << head)) && i < disp->pior.nr; i++) + ctrl = nv_rd32(disp, 0x610b84 + (i * 8)); i += 8; } @@ -1477,10 +1477,10 @@ exec_script(struct nv50_disp_priv *priv, int head, int id) return NULL; i--; - outp = exec_lookup(priv, head, i, ctrl, &data, &ver, &hdr, &cnt, &len, &info); + outp = exec_lookup(disp, head, i, ctrl, &data, &ver, &hdr, &cnt, &len, &info); if (outp) { struct nvbios_init init = { - .subdev = nv_subdev(priv), + .subdev = nv_subdev(disp), .bios = bios, .offset = info.script[id], .outp = &outp->info, @@ -1495,9 +1495,9 @@ exec_script(struct nv50_disp_priv *priv, int head, int id) } static struct nvkm_output * -exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk, u32 *conf) +exec_clkcmp(struct nv50_disp *disp, int head, int id, u32 pclk, u32 *conf) { - struct nvkm_bios *bios = nvkm_bios(priv); + struct nvkm_bios *bios = nvkm_bios(disp); struct nvkm_output *outp; struct nvbios_outp info1; struct nvbios_ocfg info2; @@ -1507,27 +1507,27 @@ exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk, u32 *conf) int i; /* DAC */ - for (i = 0; !(ctrl & (1 << head)) && i < priv->dac.nr; i++) - ctrl = nv_rd32(priv, 0x610b58 + (i * 8)); + for (i = 0; !(ctrl & (1 << head)) && i < disp->dac.nr; i++) + ctrl = nv_rd32(disp, 0x610b58 + (i * 8)); /* SOR */ if (!(ctrl & (1 << head))) { - if (nv_device(priv)->chipset < 0x90 || - nv_device(priv)->chipset == 0x92 || - nv_device(priv)->chipset == 0xa0) { + if (nv_device(disp)->chipset < 0x90 || + nv_device(disp)->chipset == 0x92 || + nv_device(disp)->chipset == 0xa0) { reg = 0x610b70; } else { reg = 0x610794; } - for (i = 0; !(ctrl & (1 << head)) && i < priv->sor.nr; i++) - ctrl = nv_rd32(priv, reg + (i * 8)); + for (i = 0; !(ctrl & (1 << head)) && i < disp->sor.nr; i++) + ctrl = nv_rd32(disp, reg + (i * 8)); i += 4; } /* PIOR */ if (!(ctrl & (1 << head))) { - for (i = 0; !(ctrl & (1 << head)) && i < priv->pior.nr; i++) - ctrl = nv_rd32(priv, 0x610b80 + (i * 8)); + for (i = 0; !(ctrl & (1 << head)) && i < disp->pior.nr; i++) + ctrl = nv_rd32(disp, 0x610b80 + (i * 8)); i += 8; } @@ -1535,7 +1535,7 @@ exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk, u32 *conf) return NULL; i--; - outp = exec_lookup(priv, head, i, ctrl, &data, &ver, &hdr, &cnt, &len, &info1); + outp = exec_lookup(disp, head, i, ctrl, &data, &ver, &hdr, &cnt, &len, &info1); if (!outp) return NULL; @@ -1547,7 +1547,7 @@ exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk, u32 *conf) *conf |= 0x0100; break; case DCB_OUTPUT_LVDS: - *conf = priv->sor.lvdsconf; + *conf = disp->sor.lvdsconf; break; case DCB_OUTPUT_DP: *conf = (ctrl & 0x00000f00) >> 8; @@ -1567,7 +1567,7 @@ exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk, u32 *conf) data = nvbios_oclk_match(bios, info2.clkcmp[id], pclk); if (data) { struct nvbios_init init = { - .subdev = nv_subdev(priv), + .subdev = nv_subdev(disp), .bios = bios, .offset = data, .outp = &outp->info, @@ -1583,15 +1583,15 @@ exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk, u32 *conf) } static void -nv50_disp_intr_unk10_0(struct nv50_disp_priv *priv, int head) +nv50_disp_intr_unk10_0(struct nv50_disp *disp, int head) { - exec_script(priv, head, 1); + exec_script(disp, head, 1); } static void -nv50_disp_intr_unk20_0(struct nv50_disp_priv *priv, int head) +nv50_disp_intr_unk20_0(struct nv50_disp *disp, int head) { - struct nvkm_output *outp = exec_script(priv, head, 2); + struct nvkm_output *outp = exec_script(disp, head, 2); /* the binary driver does this outside of the supervisor handling * (after the third supervisor from a detach). we (currently?) @@ -1609,8 +1609,8 @@ nv50_disp_intr_unk20_0(struct nv50_disp_priv *priv, int head) if (outp && outp->info.type == DCB_OUTPUT_DP) { struct nvkm_output_dp *outpdp = (void *)outp; struct nvbios_init init = { - .subdev = nv_subdev(priv), - .bios = nvkm_bios(priv), + .subdev = nv_subdev(disp), + .bios = nvkm_bios(disp), .outp = &outp->info, .crtc = head, .offset = outpdp->info.script[4], @@ -1623,29 +1623,29 @@ nv50_disp_intr_unk20_0(struct nv50_disp_priv *priv, int head) } static void -nv50_disp_intr_unk20_1(struct nv50_disp_priv *priv, int head) +nv50_disp_intr_unk20_1(struct nv50_disp *disp, int head) { - struct nvkm_devinit *devinit = nvkm_devinit(priv); - u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff; + struct nvkm_devinit *devinit = nvkm_devinit(disp); + u32 pclk = nv_rd32(disp, 0x610ad0 + (head * 0x540)) & 0x3fffff; if (pclk) devinit->pll_set(devinit, PLL_VPLL0 + head, pclk); } static void -nv50_disp_intr_unk20_2_dp(struct nv50_disp_priv *priv, int head, +nv50_disp_intr_unk20_2_dp(struct nv50_disp *disp, int head, struct dcb_output *outp, u32 pclk) { const int link = !(outp->sorconf.link & 1); const int or = ffs(outp->or) - 1; const u32 soff = ( or * 0x800); const u32 loff = (link * 0x080) + soff; - const u32 ctrl = nv_rd32(priv, 0x610794 + (or * 8)); + const u32 ctrl = nv_rd32(disp, 0x610794 + (or * 8)); const u32 symbol = 100000; - const s32 vactive = nv_rd32(priv, 0x610af8 + (head * 0x540)) & 0xffff; - const s32 vblanke = nv_rd32(priv, 0x610ae8 + (head * 0x540)) & 0xffff; - const s32 vblanks = nv_rd32(priv, 0x610af0 + (head * 0x540)) & 0xffff; - u32 dpctrl = nv_rd32(priv, 0x61c10c + loff); - u32 clksor = nv_rd32(priv, 0x614300 + soff); + const s32 vactive = nv_rd32(disp, 0x610af8 + (head * 0x540)) & 0xffff; + const s32 vblanke = nv_rd32(disp, 0x610ae8 + (head * 0x540)) & 0xffff; + const s32 vblanks = nv_rd32(disp, 0x610af0 + (head * 0x540)) & 0xffff; + u32 dpctrl = nv_rd32(disp, 0x61c10c + loff); + u32 clksor = nv_rd32(disp, 0x614300 + soff); int bestTU = 0, bestVTUi = 0, bestVTUf = 0, bestVTUa = 0; int TU, VTUi, VTUf, VTUa; u64 link_data_rate, link_ratio, unk; @@ -1661,14 +1661,14 @@ nv50_disp_intr_unk20_2_dp(struct nv50_disp_priv *priv, int head, value = value * link_bw; do_div(value, pclk); value = value - (3 * !!(dpctrl & 0x00004000)) - (12 / link_nr); - nv_mask(priv, 0x61c1e8 + soff, 0x0000ffff, value); + nv_mask(disp, 0x61c1e8 + soff, 0x0000ffff, value); /* symbols/vblank - algorithm taken from comments in tegra driver */ value = vblanks - vblanke - 25; value = value * link_bw; do_div(value, pclk); value = value - ((36 / link_nr) + 3) - 1; - nv_mask(priv, 0x61c1ec + soff, 0x00ffffff, value); + nv_mask(disp, 0x61c1ec + soff, 0x00ffffff, value); /* watermark / activesym */ if ((ctrl & 0xf0000) == 0x60000) bits = 30; @@ -1733,7 +1733,7 @@ nv50_disp_intr_unk20_2_dp(struct nv50_disp_priv *priv, int head, } if (!bestTU) { - nv_error(priv, "unable to find suitable dp config\n"); + nv_error(disp, "unable to find suitable dp config\n"); return; } @@ -1744,22 +1744,22 @@ nv50_disp_intr_unk20_2_dp(struct nv50_disp_priv *priv, int head, do_div(unk, symbol); unk += 6; - nv_mask(priv, 0x61c10c + loff, 0x000001fc, bestTU << 2); - nv_mask(priv, 0x61c128 + loff, 0x010f7f3f, bestVTUa << 24 | + nv_mask(disp, 0x61c10c + loff, 0x000001fc, bestTU << 2); + nv_mask(disp, 0x61c128 + loff, 0x010f7f3f, bestVTUa << 24 | bestVTUf << 16 | bestVTUi << 8 | unk); } static void -nv50_disp_intr_unk20_2(struct nv50_disp_priv *priv, int head) +nv50_disp_intr_unk20_2(struct nv50_disp *disp, int head) { struct nvkm_output *outp; - u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff; + u32 pclk = nv_rd32(disp, 0x610ad0 + (head * 0x540)) & 0x3fffff; u32 hval, hreg = 0x614200 + (head * 0x800); u32 oval, oreg; u32 mask, conf; - outp = exec_clkcmp(priv, head, 0xff, pclk, &conf); + outp = exec_clkcmp(disp, head, 0xff, pclk, &conf); if (!outp) return; @@ -1786,10 +1786,10 @@ nv50_disp_intr_unk20_2(struct nv50_disp_priv *priv, int head) u32 ctrl, datarate; if (outp->info.location == 0) { - ctrl = nv_rd32(priv, 0x610794 + soff); + ctrl = nv_rd32(disp, 0x610794 + soff); soff = 1; } else { - ctrl = nv_rd32(priv, 0x610b80 + soff); + ctrl = nv_rd32(disp, 0x610b80 + soff); soff = 2; } @@ -1806,7 +1806,7 @@ nv50_disp_intr_unk20_2(struct nv50_disp_priv *priv, int head) ERR("link not trained before attach\n"); } - exec_clkcmp(priv, head, 0, pclk, &conf); + exec_clkcmp(disp, head, 0, pclk, &conf); if (!outp->info.location && outp->info.type == DCB_OUTPUT_ANALOG) { oreg = 0x614280 + (ffs(outp->info.or) - 1) * 0x800; @@ -1816,7 +1816,7 @@ nv50_disp_intr_unk20_2(struct nv50_disp_priv *priv, int head) } else if (!outp->info.location) { if (outp->info.type == DCB_OUTPUT_DP) - nv50_disp_intr_unk20_2_dp(priv, head, &outp->info, pclk); + nv50_disp_intr_unk20_2_dp(disp, head, &outp->info, pclk); oreg = 0x614300 + (ffs(outp->info.or) - 1) * 0x800; oval = (conf & 0x0100) ? 0x00000101 : 0x00000000; hval = 0x00000000; @@ -1828,8 +1828,8 @@ nv50_disp_intr_unk20_2(struct nv50_disp_priv *priv, int head) mask = 0x00000707; } - nv_mask(priv, hreg, 0x0000000f, hval); - nv_mask(priv, oreg, mask, oval); + nv_mask(disp, hreg, 0x0000000f, hval); + nv_mask(disp, oreg, mask, oval); } /* If programming a TMDS output on a SOR that can also be configured for @@ -1841,10 +1841,10 @@ nv50_disp_intr_unk20_2(struct nv50_disp_priv *priv, int head) * programmed for DisplayPort. */ static void -nv50_disp_intr_unk40_0_tmds(struct nv50_disp_priv *priv, +nv50_disp_intr_unk40_0_tmds(struct nv50_disp *disp, struct dcb_output *outp) { - struct nvkm_bios *bios = nvkm_bios(priv); + struct nvkm_bios *bios = nvkm_bios(disp); const int link = !(outp->sorconf.link & 1); const int or = ffs(outp->or) - 1; const u32 loff = (or * 0x800) + (link * 0x80); @@ -1853,109 +1853,106 @@ nv50_disp_intr_unk40_0_tmds(struct nv50_disp_priv *priv, u8 ver, hdr; if (dcb_outp_match(bios, DCB_OUTPUT_DP, mask, &ver, &hdr, &match)) - nv_mask(priv, 0x61c10c + loff, 0x00000001, 0x00000000); + nv_mask(disp, 0x61c10c + loff, 0x00000001, 0x00000000); } static void -nv50_disp_intr_unk40_0(struct nv50_disp_priv *priv, int head) +nv50_disp_intr_unk40_0(struct nv50_disp *disp, int head) { struct nvkm_output *outp; - u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff; + u32 pclk = nv_rd32(disp, 0x610ad0 + (head * 0x540)) & 0x3fffff; u32 conf; - outp = exec_clkcmp(priv, head, 1, pclk, &conf); + outp = exec_clkcmp(disp, head, 1, pclk, &conf); if (!outp) return; if (outp->info.location == 0 && outp->info.type == DCB_OUTPUT_TMDS) - nv50_disp_intr_unk40_0_tmds(priv, &outp->info); + nv50_disp_intr_unk40_0_tmds(disp, &outp->info); } void nv50_disp_intr_supervisor(struct work_struct *work) { - struct nv50_disp_priv *priv = - container_of(work, struct nv50_disp_priv, supervisor); - struct nv50_disp_impl *impl = (void *)nv_object(priv)->oclass; - u32 super = nv_rd32(priv, 0x610030); + struct nv50_disp *disp = + container_of(work, struct nv50_disp, supervisor); + struct nv50_disp_impl *impl = (void *)nv_object(disp)->oclass; + u32 super = nv_rd32(disp, 0x610030); int head; - nv_debug(priv, "supervisor 0x%08x 0x%08x\n", priv->super, super); + nv_debug(disp, "supervisor 0x%08x 0x%08x\n", disp->super, super); - if (priv->super & 0x00000010) { - nv50_disp_mthd_chan(priv, NV_DBG_DEBUG, 0, impl->mthd.core); - for (head = 0; head < priv->head.nr; head++) { + if (disp->super & 0x00000010) { + nv50_disp_mthd_chan(disp, NV_DBG_DEBUG, 0, impl->mthd.core); + for (head = 0; head < disp->head.nr; head++) { if (!(super & (0x00000020 << head))) continue; if (!(super & (0x00000080 << head))) continue; - nv50_disp_intr_unk10_0(priv, head); + nv50_disp_intr_unk10_0(disp, head); } } else - if (priv->super & 0x00000020) { - for (head = 0; head < priv->head.nr; head++) { + if (disp->super & 0x00000020) { + for (head = 0; head < disp->head.nr; head++) { if (!(super & (0x00000080 << head))) continue; - nv50_disp_intr_unk20_0(priv, head); + nv50_disp_intr_unk20_0(disp, head); } - for (head = 0; head < priv->head.nr; head++) { + for (head = 0; head < disp->head.nr; head++) { if (!(super & (0x00000200 << head))) continue; - nv50_disp_intr_unk20_1(priv, head); + nv50_disp_intr_unk20_1(disp, head); } - for (head = 0; head < priv->head.nr; head++) { + for (head = 0; head < disp->head.nr; head++) { if (!(super & (0x00000080 << head))) continue; - nv50_disp_intr_unk20_2(priv, head); + nv50_disp_intr_unk20_2(disp, head); } } else - if (priv->super & 0x00000040) { - for (head = 0; head < priv->head.nr; head++) { + if (disp->super & 0x00000040) { + for (head = 0; head < disp->head.nr; head++) { if (!(super & (0x00000080 << head))) continue; - nv50_disp_intr_unk40_0(priv, head); + nv50_disp_intr_unk40_0(disp, head); } } - nv_wr32(priv, 0x610030, 0x80000000); + nv_wr32(disp, 0x610030, 0x80000000); } void nv50_disp_intr(struct nvkm_subdev *subdev) { - struct nv50_disp_priv *priv = (void *)subdev; - u32 intr0 = nv_rd32(priv, 0x610020); - u32 intr1 = nv_rd32(priv, 0x610024); + struct nv50_disp *disp = (void *)subdev; + u32 intr0 = nv_rd32(disp, 0x610020); + u32 intr1 = nv_rd32(disp, 0x610024); while (intr0 & 0x001f0000) { u32 chid = __ffs(intr0 & 0x001f0000) - 16; - nv50_disp_intr_error(priv, chid); + nv50_disp_intr_error(disp, chid); intr0 &= ~(0x00010000 << chid); } while (intr0 & 0x0000001f) { u32 chid = __ffs(intr0 & 0x0000001f); - nv50_disp_chan_uevent_send(priv, chid); + nv50_disp_chan_uevent_send(disp, chid); intr0 &= ~(0x00000001 << chid); } if (intr1 & 0x00000004) { - nvkm_disp_vblank(&priv->base, 0); - nv_wr32(priv, 0x610024, 0x00000004); - intr1 &= ~0x00000004; + nvkm_disp_vblank(&disp->base, 0); + nv_wr32(disp, 0x610024, 0x00000004); } if (intr1 & 0x00000008) { - nvkm_disp_vblank(&priv->base, 1); - nv_wr32(priv, 0x610024, 0x00000008); - intr1 &= ~0x00000008; + nvkm_disp_vblank(&disp->base, 1); + nv_wr32(disp, 0x610024, 0x00000008); } if (intr1 & 0x00000070) { - priv->super = (intr1 & 0x00000070); - schedule_work(&priv->supervisor); - nv_wr32(priv, 0x610024, priv->super); - intr1 &= ~0x00000070; + disp->super = (intr1 & 0x00000070); + schedule_work(&disp->supervisor); + nv_wr32(disp, 0x610024, disp->super); } } @@ -1964,32 +1961,32 @@ nv50_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nv50_disp_priv *priv; + struct nv50_disp *disp; int ret; ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP", - "display", &priv); - *pobject = nv_object(priv); + "display", &disp); + *pobject = nv_object(disp); if (ret) return ret; - ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent); + ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &disp->uevent); if (ret) return ret; - nv_engine(priv)->sclass = nv50_disp_main_oclass; - nv_engine(priv)->cclass = &nv50_disp_cclass; - nv_subdev(priv)->intr = nv50_disp_intr; - INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor); - priv->sclass = nv50_disp_sclass; - priv->head.nr = 2; - priv->dac.nr = 3; - priv->sor.nr = 2; - priv->pior.nr = 3; - priv->dac.power = nv50_dac_power; - priv->dac.sense = nv50_dac_sense; - priv->sor.power = nv50_sor_power; - priv->pior.power = nv50_pior_power; + nv_engine(disp)->sclass = nv50_disp_main_oclass; + nv_engine(disp)->cclass = &nv50_disp_cclass; + nv_subdev(disp)->intr = nv50_disp_intr; + INIT_WORK(&disp->supervisor, nv50_disp_intr_supervisor); + disp->sclass = nv50_disp_sclass; + disp->head.nr = 2; + disp->dac.nr = 3; + disp->sor.nr = 2; + disp->pior.nr = 3; + disp->dac.power = nv50_dac_power; + disp->dac.sense = nv50_dac_sense; + disp->sor.power = nv50_sor_power; + disp->pior.power = nv50_pior_power; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h index b9dfa660e7dd..24d3413defbd 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h @@ -5,11 +5,11 @@ struct nvkm_output; struct nvkm_output_dp; #define NV50_DISP_MTHD_ struct nvkm_object *object, \ - struct nv50_disp_priv *priv, void *data, u32 size + struct nv50_disp *disp, void *data, u32 size #define NV50_DISP_MTHD_V0 NV50_DISP_MTHD_, int head #define NV50_DISP_MTHD_V1 NV50_DISP_MTHD_, int head, struct nvkm_output *outp -struct nv50_disp_priv { +struct nv50_disp { struct nvkm_disp base; struct nvkm_oclass *sclass; @@ -102,7 +102,7 @@ void nv50_disp_chan_wr32(struct nvkm_object *, u64, u32); extern const struct nvkm_event_func nv50_disp_chan_uevent; int nv50_disp_chan_uevent_ctor(struct nvkm_object *, void *, u32, struct nvkm_notify *); -void nv50_disp_chan_uevent_send(struct nv50_disp_priv *, int); +void nv50_disp_chan_uevent_send(struct nv50_disp *, int); extern const struct nvkm_event_func gf110_disp_chan_uevent; @@ -177,7 +177,7 @@ int nv50_disp_main_ctor(struct nvkm_object *, struct nvkm_object *, void nv50_disp_main_dtor(struct nvkm_object *); extern struct nvkm_omthds nv50_disp_main_omthds[]; extern struct nvkm_oclass nv50_disp_cclass; -void nv50_disp_mthd_chan(struct nv50_disp_priv *, int debug, int head, +void nv50_disp_mthd_chan(struct nv50_disp *, int debug, int head, const struct nv50_disp_mthd_chan *); void nv50_disp_intr_supervisor(struct work_struct *); void nv50_disp_intr(struct nvkm_subdev *); @@ -214,7 +214,7 @@ extern struct nvkm_output_dp_impl nv50_pior_dp_impl; extern struct nvkm_oclass *nv50_disp_outp_sclass[]; extern struct nvkm_output_dp_impl g94_sor_dp_impl; -u32 g94_sor_dp_lane_map(struct nv50_disp_priv *, u8 lane); +u32 g94_sor_dp_lane_map(struct nv50_disp *, u8 lane); int g94_sor_dp_lnk_pwr(struct nvkm_output_dp *, int); extern struct nvkm_oclass *g94_disp_outp_sclass[]; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c index 2a1d8871bf82..94f0b4d2c890 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c @@ -162,9 +162,9 @@ nv50_pior_power(NV50_DISP_MTHD_V1) } else return ret; - nv_wait(priv, 0x61e004 + soff, 0x80000000, 0x00000000); - nv_mask(priv, 0x61e004 + soff, 0x80000101, 0x80000000 | ctrl); - nv_wait(priv, 0x61e004 + soff, 0x80000000, 0x00000000); - priv->pior.type[outp->or] = type; + nv_wait(disp, 0x61e004 + soff, 0x80000000, 0x00000000); + nv_mask(disp, 0x61e004 + soff, 0x80000101, 0x80000000 | ctrl); + nv_wait(disp, 0x61e004 + soff, 0x80000000, 0x00000000); + disp->pior.type[outp->or] = type; return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c index 0b4ecb837597..b4138acc94de 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c @@ -39,14 +39,14 @@ g94_sor_loff(struct nvkm_output_dp *outp) } u32 -g94_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane) +g94_sor_dp_lane_map(struct nv50_disp *disp, u8 lane) { static const u8 gm100[] = { 0, 8, 16, 24 }; static const u8 mcp89[] = { 24, 16, 8, 0 }; /* thanks, apple.. */ static const u8 g94[] = { 16, 8, 0, 24 }; - if (nv_device(priv)->chipset >= 0x110) + if (nv_device(disp)->chipset >= 0x110) return gm100[lane]; - if (nv_device(priv)->chipset == 0xaf) + if (nv_device(disp)->chipset == 0xaf) return mcp89[lane]; return g94[lane]; } @@ -54,33 +54,33 @@ g94_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane) static int g94_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern) { - struct nv50_disp_priv *priv = (void *)nvkm_disp(outp); + struct nv50_disp *disp = (void *)nvkm_disp(outp); const u32 loff = g94_sor_loff(outp); - nv_mask(priv, 0x61c10c + loff, 0x0f000000, pattern << 24); + nv_mask(disp, 0x61c10c + loff, 0x0f000000, pattern << 24); return 0; } int g94_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr) { - struct nv50_disp_priv *priv = (void *)nvkm_disp(outp); + struct nv50_disp *disp = (void *)nvkm_disp(outp); const u32 soff = g94_sor_soff(outp); const u32 loff = g94_sor_loff(outp); u32 mask = 0, i; for (i = 0; i < nr; i++) - mask |= 1 << (g94_sor_dp_lane_map(priv, i) >> 3); + mask |= 1 << (g94_sor_dp_lane_map(disp, i) >> 3); - nv_mask(priv, 0x61c130 + loff, 0x0000000f, mask); - nv_mask(priv, 0x61c034 + soff, 0x80000000, 0x80000000); - nv_wait(priv, 0x61c034 + soff, 0x80000000, 0x00000000); + nv_mask(disp, 0x61c130 + loff, 0x0000000f, mask); + nv_mask(disp, 0x61c034 + soff, 0x80000000, 0x80000000); + nv_wait(disp, 0x61c034 + soff, 0x80000000, 0x00000000); return 0; } static int g94_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef) { - struct nv50_disp_priv *priv = (void *)nvkm_disp(outp); + struct nv50_disp *disp = (void *)nvkm_disp(outp); const u32 soff = g94_sor_soff(outp); const u32 loff = g94_sor_loff(outp); u32 dpctrl = 0x00000000; @@ -92,17 +92,17 @@ g94_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef) if (bw > 0x06) clksor |= 0x00040000; - nv_mask(priv, 0x614300 + soff, 0x000c0000, clksor); - nv_mask(priv, 0x61c10c + loff, 0x001f4000, dpctrl); + nv_mask(disp, 0x614300 + soff, 0x000c0000, clksor); + nv_mask(disp, 0x61c10c + loff, 0x001f4000, dpctrl); return 0; } static int g94_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc) { - struct nv50_disp_priv *priv = (void *)nvkm_disp(outp); - struct nvkm_bios *bios = nvkm_bios(priv); - const u32 shift = g94_sor_dp_lane_map(priv, ln); + struct nv50_disp *disp = (void *)nvkm_disp(outp); + struct nvkm_bios *bios = nvkm_bios(disp); + const u32 shift = g94_sor_dp_lane_map(disp, ln); const u32 loff = g94_sor_loff(outp); u32 addr, data[3]; u8 ver, hdr, cnt, len; @@ -120,14 +120,14 @@ g94_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc) if (!addr) return -EINVAL; - data[0] = nv_rd32(priv, 0x61c118 + loff) & ~(0x000000ff << shift); - data[1] = nv_rd32(priv, 0x61c120 + loff) & ~(0x000000ff << shift); - data[2] = nv_rd32(priv, 0x61c130 + loff); + data[0] = nv_rd32(disp, 0x61c118 + loff) & ~(0x000000ff << shift); + data[1] = nv_rd32(disp, 0x61c120 + loff) & ~(0x000000ff << shift); + data[2] = nv_rd32(disp, 0x61c130 + loff); if ((data[2] & 0x0000ff00) < (ocfg.tx_pu << 8) || ln == 0) data[2] = (data[2] & ~0x0000ff00) | (ocfg.tx_pu << 8); - nv_wr32(priv, 0x61c118 + loff, data[0] | (ocfg.dc << shift)); - nv_wr32(priv, 0x61c120 + loff, data[1] | (ocfg.pe << shift)); - nv_wr32(priv, 0x61c130 + loff, data[2]); + nv_wr32(disp, 0x61c118 + loff, data[0] | (ocfg.dc << shift)); + nv_wr32(disp, 0x61c120 + loff, data[1] | (ocfg.pe << shift)); + nv_wr32(disp, 0x61c130 + loff, data[2]); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf110.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf110.c index 1f02b603e19a..07dbe45996c7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf110.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf110.c @@ -39,16 +39,16 @@ gf110_sor_loff(struct nvkm_output_dp *outp) static int gf110_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern) { - struct nv50_disp_priv *priv = (void *)nvkm_disp(outp); + struct nv50_disp *disp = (void *)nvkm_disp(outp); const u32 loff = gf110_sor_loff(outp); - nv_mask(priv, 0x61c110 + loff, 0x0f0f0f0f, 0x01010101 * pattern); + nv_mask(disp, 0x61c110 + loff, 0x0f0f0f0f, 0x01010101 * pattern); return 0; } int gf110_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef) { - struct nv50_disp_priv *priv = (void *)nvkm_disp(outp); + struct nv50_disp *disp = (void *)nvkm_disp(outp); const u32 soff = gf110_sor_soff(outp); const u32 loff = gf110_sor_loff(outp); u32 dpctrl = 0x00000000; @@ -59,8 +59,8 @@ gf110_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef) if (ef) dpctrl |= 0x00004000; - nv_mask(priv, 0x612300 + soff, 0x007c0000, clksor); - nv_mask(priv, 0x61c10c + loff, 0x001f4000, dpctrl); + nv_mask(disp, 0x612300 + soff, 0x007c0000, clksor); + nv_mask(disp, 0x61c10c + loff, 0x001f4000, dpctrl); return 0; } @@ -68,9 +68,9 @@ static int gf110_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc) { - struct nv50_disp_priv *priv = (void *)nvkm_disp(outp); - struct nvkm_bios *bios = nvkm_bios(priv); - const u32 shift = g94_sor_dp_lane_map(priv, ln); + struct nv50_disp *disp = (void *)nvkm_disp(outp); + struct nvkm_bios *bios = nvkm_bios(disp); + const u32 shift = g94_sor_dp_lane_map(disp, ln); const u32 loff = gf110_sor_loff(outp); u32 addr, data[4]; u8 ver, hdr, cnt, len; @@ -88,16 +88,16 @@ gf110_sor_dp_drv_ctl(struct nvkm_output_dp *outp, if (!addr) return -EINVAL; - data[0] = nv_rd32(priv, 0x61c118 + loff) & ~(0x000000ff << shift); - data[1] = nv_rd32(priv, 0x61c120 + loff) & ~(0x000000ff << shift); - data[2] = nv_rd32(priv, 0x61c130 + loff); + data[0] = nv_rd32(disp, 0x61c118 + loff) & ~(0x000000ff << shift); + data[1] = nv_rd32(disp, 0x61c120 + loff) & ~(0x000000ff << shift); + data[2] = nv_rd32(disp, 0x61c130 + loff); if ((data[2] & 0x0000ff00) < (ocfg.tx_pu << 8) || ln == 0) data[2] = (data[2] & ~0x0000ff00) | (ocfg.tx_pu << 8); - nv_wr32(priv, 0x61c118 + loff, data[0] | (ocfg.dc << shift)); - nv_wr32(priv, 0x61c120 + loff, data[1] | (ocfg.pe << shift)); - nv_wr32(priv, 0x61c130 + loff, data[2]); - data[3] = nv_rd32(priv, 0x61c13c + loff) & ~(0x000000ff << shift); - nv_wr32(priv, 0x61c13c + loff, data[3] | (ocfg.pc << shift)); + nv_wr32(disp, 0x61c118 + loff, data[0] | (ocfg.dc << shift)); + nv_wr32(disp, 0x61c120 + loff, data[1] | (ocfg.pe << shift)); + nv_wr32(disp, 0x61c130 + loff, data[2]); + data[3] = nv_rd32(disp, 0x61c13c + loff) & ~(0x000000ff << shift); + nv_wr32(disp, 0x61c13c + loff, data[3] | (ocfg.pc << shift)); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm204.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm204.c index a2706e24f5c1..3078f4d91972 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm204.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm204.c @@ -41,17 +41,17 @@ gm204_sor_loff(struct nvkm_output_dp *outp) void gm204_sor_magic(struct nvkm_output *outp) { - struct nv50_disp_priv *priv = (void *)nvkm_disp(outp); + struct nv50_disp *disp = (void *)nvkm_disp(outp); const u32 soff = outp->or * 0x100; const u32 data = outp->or + 1; if (outp->info.sorconf.link & 1) - nv_mask(priv, 0x612308 + soff, 0x0000001f, 0x00000000 | data); + nv_mask(disp, 0x612308 + soff, 0x0000001f, 0x00000000 | data); if (outp->info.sorconf.link & 2) - nv_mask(priv, 0x612388 + soff, 0x0000001f, 0x00000010 | data); + nv_mask(disp, 0x612388 + soff, 0x0000001f, 0x00000010 | data); } static inline u32 -gm204_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane) +gm204_sor_dp_lane_map(struct nv50_disp *disp, u8 lane) { return lane * 0x08; } @@ -59,30 +59,30 @@ gm204_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane) static int gm204_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern) { - struct nv50_disp_priv *priv = (void *)nvkm_disp(outp); + struct nv50_disp *disp = (void *)nvkm_disp(outp); const u32 soff = gm204_sor_soff(outp); const u32 data = 0x01010101 * pattern; if (outp->base.info.sorconf.link & 1) - nv_mask(priv, 0x61c110 + soff, 0x0f0f0f0f, data); + nv_mask(disp, 0x61c110 + soff, 0x0f0f0f0f, data); else - nv_mask(priv, 0x61c12c + soff, 0x0f0f0f0f, data); + nv_mask(disp, 0x61c12c + soff, 0x0f0f0f0f, data); return 0; } static int gm204_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr) { - struct nv50_disp_priv *priv = (void *)nvkm_disp(outp); + struct nv50_disp *disp = (void *)nvkm_disp(outp); const u32 soff = gm204_sor_soff(outp); const u32 loff = gm204_sor_loff(outp); u32 mask = 0, i; for (i = 0; i < nr; i++) - mask |= 1 << (gm204_sor_dp_lane_map(priv, i) >> 3); + mask |= 1 << (gm204_sor_dp_lane_map(disp, i) >> 3); - nv_mask(priv, 0x61c130 + loff, 0x0000000f, mask); - nv_mask(priv, 0x61c034 + soff, 0x80000000, 0x80000000); - nv_wait(priv, 0x61c034 + soff, 0x80000000, 0x00000000); + nv_mask(disp, 0x61c130 + loff, 0x0000000f, mask); + nv_mask(disp, 0x61c034 + soff, 0x80000000, 0x80000000); + nv_wait(disp, 0x61c034 + soff, 0x80000000, 0x00000000); return 0; } @@ -90,9 +90,9 @@ static int gm204_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc) { - struct nv50_disp_priv *priv = (void *)nvkm_disp(outp); - struct nvkm_bios *bios = nvkm_bios(priv); - const u32 shift = gm204_sor_dp_lane_map(priv, ln); + struct nv50_disp *disp = (void *)nvkm_disp(outp); + struct nvkm_bios *bios = nvkm_bios(disp); + const u32 shift = gm204_sor_dp_lane_map(disp, ln); const u32 loff = gm204_sor_loff(outp); u32 addr, data[4]; u8 ver, hdr, cnt, len; @@ -111,16 +111,16 @@ gm204_sor_dp_drv_ctl(struct nvkm_output_dp *outp, return -EINVAL; ocfg.tx_pu &= 0x0f; - data[0] = nv_rd32(priv, 0x61c118 + loff) & ~(0x000000ff << shift); - data[1] = nv_rd32(priv, 0x61c120 + loff) & ~(0x000000ff << shift); - data[2] = nv_rd32(priv, 0x61c130 + loff); + data[0] = nv_rd32(disp, 0x61c118 + loff) & ~(0x000000ff << shift); + data[1] = nv_rd32(disp, 0x61c120 + loff) & ~(0x000000ff << shift); + data[2] = nv_rd32(disp, 0x61c130 + loff); if ((data[2] & 0x00000f00) < (ocfg.tx_pu << 8) || ln == 0) data[2] = (data[2] & ~0x00000f00) | (ocfg.tx_pu << 8); - nv_wr32(priv, 0x61c118 + loff, data[0] | (ocfg.dc << shift)); - nv_wr32(priv, 0x61c120 + loff, data[1] | (ocfg.pe << shift)); - nv_wr32(priv, 0x61c130 + loff, data[2]); - data[3] = nv_rd32(priv, 0x61c13c + loff) & ~(0x000000ff << shift); - nv_wr32(priv, 0x61c13c + loff, data[3] | (ocfg.pc << shift)); + nv_wr32(disp, 0x61c118 + loff, data[0] | (ocfg.dc << shift)); + nv_wr32(disp, 0x61c120 + loff, data[1] | (ocfg.pe << shift)); + nv_wr32(disp, 0x61c130 + loff, data[2]); + data[3] = nv_rd32(disp, 0x61c13c + loff) & ~(0x000000ff << shift); + nv_wr32(disp, 0x61c13c + loff, data[3] | (ocfg.pc << shift)); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c index b229a311c78c..74ad5921b230 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c @@ -48,9 +48,9 @@ nv50_sor_power(NV50_DISP_MTHD_V1) } else return ret; - nv_wait(priv, 0x61c004 + soff, 0x80000000, 0x00000000); - nv_mask(priv, 0x61c004 + soff, 0x80000001, 0x80000000 | stat); - nv_wait(priv, 0x61c004 + soff, 0x80000000, 0x00000000); - nv_wait(priv, 0x61c030 + soff, 0x10000000, 0x00000000); + nv_wait(disp, 0x61c004 + soff, 0x80000000, 0x00000000); + nv_mask(disp, 0x61c004 + soff, 0x80000001, 0x80000000 | stat); + nv_wait(disp, 0x61c004 + soff, 0x80000000, 0x00000000); + nv_wait(disp, 0x61c030 + soff, 0x10000000, 0x00000000); return 0; } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c index 14d9650f4779..0946280a54b0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c @@ -156,7 +156,7 @@ nv50_sw_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, struct nvkm_object **pobject) { - struct nvkm_disp *pdisp = nvkm_disp(parent); + struct nvkm_disp *disp = nvkm_disp(parent); struct nv50_sw_cclass *pclass = (void *)oclass; struct nv50_sw_chan *chan; int ret, i; @@ -166,8 +166,8 @@ nv50_sw_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, if (ret) return ret; - for (i = 0; pdisp && i < pdisp->vblank.index_nr; i++) { - ret = nvkm_notify_init(NULL, &pdisp->vblank, pclass->vblank, + for (i = 0; disp && i < disp->vblank.index_nr; i++) { + ret = nvkm_notify_init(NULL, &disp->vblank, pclass->vblank, false, &(struct nvif_notify_head_req_v0) { .head = i, -- 2.39.5