ARM: dts: imx6qdl: rename pinctrl_pwm0 for consistency

[karo-tx-linux.git] / arch / arm / boot / dts / imx6qdl.dtsi

diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 226ce75c87a8d24ab0da3e5bcd4c27a980134925..ea666818a90b1bf6e48ab6106d057fe4b56bbdbb 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -647,6 +647,15 @@
                                                        MX6QDL_PAD_DISP0_DAT19__AUD5_RXD  0x80000000
                                                >;
                                        };
+
+                                       pinctrl_audmux_5: audmux-5 {
+                                               fsl,pins = <
+                                                       MX6QDL_PAD_KEY_ROW1__AUD5_RXD  0x80000000
+                                                       MX6QDL_PAD_KEY_ROW0__AUD5_TXD  0x80000000
+                                                       MX6QDL_PAD_KEY_COL0__AUD5_TXC  0x80000000
+                                                       MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x80000000
+                                               >;
+                                       };
                                };
 
                                ecspi1 {
@@ -739,6 +748,20 @@
                                                        MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN     0x1b0b0
                                                >;
                                        };
+
+                                       pinctrl_enet_4: enetgrp-4 {
+                                               fsl,pins = <
+                                                       MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
+                                                       MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
+                                                       MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0   0x1b0b0
+                                                       MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1   0x1b0b0
+                                                       MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER     0x1b0b0
+                                                       MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN     0x1b0b0
+                                                       MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0   0x1b0b0
+                                                       MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1   0x1b0b0
+                                                       MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN    0x1b0b0
+                                               >;
+                                       };
                                };
 
                                esai {
@@ -786,6 +809,13 @@
                                                        MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
                                                >;
                                        };
+
+                                       pinctrl_flexcan1_3: flexcan1grp-3 {
+                                               fsl,pins = <
+                                                       MX6QDL_PAD_GPIO_7__FLEXCAN1_TX   0x80000000
+                                                       MX6QDL_PAD_GPIO_8__FLEXCAN1_RX   0x80000000
+                                               >;
+                                       };
                                };
 
                                flexcan2 {
@@ -1044,8 +1074,8 @@
                                        };
                                };
 
-                               pwm0 {
-                                       pinctrl_pwm0_1: pwm0grp-1 {
+                               pwm1 {
+                                       pinctrl_pwm1_1: pwm1grp-1 {
                                                fsl,pins = <
                                                        MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
                                                >;
@@ -1147,6 +1177,13 @@
                                                        MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
                                                >;
                                        };
+
+                                       pinctrl_uart3_rtscts_3: uart3rtscts-3 {
+                                               fsl,pins = <
+                                                       MX6QDL_PAD_SD3_DAT3__UART3_CTS_B  0x1b0b1
+                                                       MX6QDL_PAD_SD3_RST__UART3_RTS_B   0x1b0b1
+                                               >;
+                                       };
                                };
 
                                uart4 {