MLK-9961-3 arm:dts:imx6x: Change PLL1 clock management.

[karo-tx-linux.git] / arch / arm / boot / dts / imx6sl.dtsi

diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 073c731fa8bb00db7fdb4808ea3648c4d2afb2e5..1b1e5f319c9372e36de09ab49d2fb736bfe4652c 100644 (file)
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -61,9 +61,12 @@
                        clock-latency = <61036>; /* two CLK32 periods */
                        clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
                                        <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
-                                       <&clks IMX6SL_CLK_PLL1_SYS>;
+                                       <&clks IMX6SL_CLK_PLL1_SYS>,
+                                       <&clks IMX6SL_PLL1_BYPASS>,
+                                       <&clks IMX6SL_CLK_PLL1>,
+                                       <&clks IMX6SL_PLL1_BYPASS_SRC> ;
                        clock-names = "arm", "pll2_pfd2_396m", "step",
-                                     "pll1_sw", "pll1_sys";
+                                     "pll1_sw", "pll1_sys", "pll1_bypass", "pll1", "pll1_bypass_src";
                        arm-supply = <&reg_arm>;
                        pu-supply = <&reg_pu>;
                        soc-supply = <&reg_soc>;
@@ -118,11 +121,12 @@
                                        <&clks IMX6SL_CLK_PLL1_SW>, <&clks IMX6SL_CLK_PRE_PERIPH2_SEL>,
                                        <&clks IMX6SL_CLK_PERIPH2_CLK2_SEL>, <&clks IMX6SL_CLK_PERIPH2_CLK2_PODF>,
                                        <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_PLL2_BYPASS_SRC>, <&clks IMX6SL_PLL2_BYPASS>,
-                                       <&clks IMX6SL_CLK_PLL2>;
+                                       <&clks IMX6SL_CLK_PLL2>, <&clks IMX6SL_CLK_PLL1>, <&clks IMX6SL_PLL1_BYPASS>,
+                                       <&clks IMX6SL_PLL1_BYPASS_SRC>;
                        clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph",
                                "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "pll1_sys", "periph2", "ahb",
                                "ocram", "pll1_sw", "periph2_pre", "periph2_clk2_sel", "periph2_clk2", "step", "pll2_bypass_src",
-                               "pll2_bypass", "pll2";
+                               "pll2_bypass", "pll2", "pll1", "pll1_bypass", "pll1_bypass_src";
                        fsl,max_ddr_freq = <400000000>;
                };