Merge branch 'late/clksrc' into late/cleanup

[karo-tx-linux.git] / drivers / clk / spear / spear1340_clock.c

diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c
index 35e7e2698e100fad879337e1b44823edfddb7a18..9d0b3949db30da927ce37d45aa4ca4eafe9c4cfe 100644 (file)
--- a/drivers/clk/spear/spear1340_clock.c
+++ b/drivers/clk/spear/spear1340_clock.c
@@ -17,18 +17,17 @@
 #include <linux/io.h>
 #include <linux/of_platform.h>
 #include <linux/spinlock_types.h>
-#include <mach/spear.h>
 #include "clk.h"
 
 /* Clock Configuration Registers */
-#define SPEAR1340_SYS_CLK_CTRL                 (VA_MISC_BASE + 0x200)
+#define SPEAR1340_SYS_CLK_CTRL                 (misc_base + 0x200)
        #define SPEAR1340_HCLK_SRC_SEL_SHIFT    27
        #define SPEAR1340_HCLK_SRC_SEL_MASK     1
        #define SPEAR1340_SCLK_SRC_SEL_SHIFT    23
        #define SPEAR1340_SCLK_SRC_SEL_MASK     3
 
 /* PLL related registers and bit values */
-#define SPEAR1340_PLL_CFG                      (VA_MISC_BASE + 0x210)
+#define SPEAR1340_PLL_CFG                      (misc_base + 0x210)
        /* PLL_CFG bit values */
        #define SPEAR1340_CLCD_SYNT_CLK_MASK            1
        #define SPEAR1340_CLCD_SYNT_CLK_SHIFT           31
@@ -40,15 +39,15 @@
        #define SPEAR1340_PLL2_CLK_SHIFT                22
        #define SPEAR1340_PLL1_CLK_SHIFT                20
 
-#define SPEAR1340_PLL1_CTR                     (VA_MISC_BASE + 0x214)
-#define SPEAR1340_PLL1_FRQ                     (VA_MISC_BASE + 0x218)
-#define SPEAR1340_PLL2_CTR                     (VA_MISC_BASE + 0x220)
-#define SPEAR1340_PLL2_FRQ                     (VA_MISC_BASE + 0x224)
-#define SPEAR1340_PLL3_CTR                     (VA_MISC_BASE + 0x22C)
-#define SPEAR1340_PLL3_FRQ                     (VA_MISC_BASE + 0x230)
-#define SPEAR1340_PLL4_CTR                     (VA_MISC_BASE + 0x238)
-#define SPEAR1340_PLL4_FRQ                     (VA_MISC_BASE + 0x23C)
-#define SPEAR1340_PERIP_CLK_CFG                        (VA_MISC_BASE + 0x244)
+#define SPEAR1340_PLL1_CTR                     (misc_base + 0x214)
+#define SPEAR1340_PLL1_FRQ                     (misc_base + 0x218)
+#define SPEAR1340_PLL2_CTR                     (misc_base + 0x220)
+#define SPEAR1340_PLL2_FRQ                     (misc_base + 0x224)
+#define SPEAR1340_PLL3_CTR                     (misc_base + 0x22C)
+#define SPEAR1340_PLL3_FRQ                     (misc_base + 0x230)
+#define SPEAR1340_PLL4_CTR                     (misc_base + 0x238)
+#define SPEAR1340_PLL4_FRQ                     (misc_base + 0x23C)
+#define SPEAR1340_PERIP_CLK_CFG                        (misc_base + 0x244)
        /* PERIP_CLK_CFG bit values */
        #define SPEAR1340_SPDIF_CLK_MASK                1
        #define SPEAR1340_SPDIF_OUT_CLK_SHIFT           15
@@ -66,13 +65,13 @@
        #define SPEAR1340_C3_CLK_MASK                   1
        #define SPEAR1340_C3_CLK_SHIFT                  1
 
-#define SPEAR1340_GMAC_CLK_CFG                 (VA_MISC_BASE + 0x248)
+#define SPEAR1340_GMAC_CLK_CFG                 (misc_base + 0x248)
        #define SPEAR1340_GMAC_PHY_CLK_MASK             1
        #define SPEAR1340_GMAC_PHY_CLK_SHIFT            2
        #define SPEAR1340_GMAC_PHY_INPUT_CLK_MASK       2
        #define SPEAR1340_GMAC_PHY_INPUT_CLK_SHIFT      0
 
-#define SPEAR1340_I2S_CLK_CFG                  (VA_MISC_BASE + 0x24C)
+#define SPEAR1340_I2S_CLK_CFG                  (misc_base + 0x24C)
        /* I2S_CLK_CFG register mask */
        #define SPEAR1340_I2S_SCLK_X_MASK               0x1F
        #define SPEAR1340_I2S_SCLK_X_SHIFT              27
@@ -90,21 +89,21 @@
        #define SPEAR1340_I2S_SRC_CLK_MASK              2
        #define SPEAR1340_I2S_SRC_CLK_SHIFT             0
 
-#define SPEAR1340_C3_CLK_SYNT                  (VA_MISC_BASE + 0x250)
-#define SPEAR1340_UART0_CLK_SYNT               (VA_MISC_BASE + 0x254)
-#define SPEAR1340_UART1_CLK_SYNT               (VA_MISC_BASE + 0x258)
-#define SPEAR1340_GMAC_CLK_SYNT                        (VA_MISC_BASE + 0x25C)
-#define SPEAR1340_SDHCI_CLK_SYNT               (VA_MISC_BASE + 0x260)
-#define SPEAR1340_CFXD_CLK_SYNT                        (VA_MISC_BASE + 0x264)
-#define SPEAR1340_ADC_CLK_SYNT                 (VA_MISC_BASE + 0x270)
-#define SPEAR1340_AMBA_CLK_SYNT                        (VA_MISC_BASE + 0x274)
-#define SPEAR1340_CLCD_CLK_SYNT                        (VA_MISC_BASE + 0x27C)
-#define SPEAR1340_SYS_CLK_SYNT                 (VA_MISC_BASE + 0x284)
-#define SPEAR1340_GEN_CLK_SYNT0                        (VA_MISC_BASE + 0x28C)
-#define SPEAR1340_GEN_CLK_SYNT1                        (VA_MISC_BASE + 0x294)
-#define SPEAR1340_GEN_CLK_SYNT2                        (VA_MISC_BASE + 0x29C)
-#define SPEAR1340_GEN_CLK_SYNT3                        (VA_MISC_BASE + 0x304)
-#define SPEAR1340_PERIP1_CLK_ENB               (VA_MISC_BASE + 0x30C)
+#define SPEAR1340_C3_CLK_SYNT                  (misc_base + 0x250)
+#define SPEAR1340_UART0_CLK_SYNT               (misc_base + 0x254)
+#define SPEAR1340_UART1_CLK_SYNT               (misc_base + 0x258)
+#define SPEAR1340_GMAC_CLK_SYNT                        (misc_base + 0x25C)
+#define SPEAR1340_SDHCI_CLK_SYNT               (misc_base + 0x260)
+#define SPEAR1340_CFXD_CLK_SYNT                        (misc_base + 0x264)
+#define SPEAR1340_ADC_CLK_SYNT                 (misc_base + 0x270)
+#define SPEAR1340_AMBA_CLK_SYNT                        (misc_base + 0x274)
+#define SPEAR1340_CLCD_CLK_SYNT                        (misc_base + 0x27C)
+#define SPEAR1340_SYS_CLK_SYNT                 (misc_base + 0x284)
+#define SPEAR1340_GEN_CLK_SYNT0                        (misc_base + 0x28C)
+#define SPEAR1340_GEN_CLK_SYNT1                        (misc_base + 0x294)
+#define SPEAR1340_GEN_CLK_SYNT2                        (misc_base + 0x29C)
+#define SPEAR1340_GEN_CLK_SYNT3                        (misc_base + 0x304)
+#define SPEAR1340_PERIP1_CLK_ENB               (misc_base + 0x30C)
        #define SPEAR1340_RTC_CLK_ENB                   31
        #define SPEAR1340_ADC_CLK_ENB                   30
        #define SPEAR1340_C3_CLK_ENB                    29
@@ -133,7 +132,7 @@
        #define SPEAR1340_SYSROM_CLK_ENB                1
        #define SPEAR1340_BUS_CLK_ENB                   0
 
-#define SPEAR1340_PERIP2_CLK_ENB               (VA_MISC_BASE + 0x310)
+#define SPEAR1340_PERIP2_CLK_ENB               (misc_base + 0x310)
        #define SPEAR1340_THSENS_CLK_ENB                8
        #define SPEAR1340_I2S_REF_PAD_CLK_ENB           7
        #define SPEAR1340_ACP_CLK_ENB                   6
@@ -144,7 +143,7 @@
        #define SPEAR1340_DDR_CORE_CLK_ENB              1
        #define SPEAR1340_DDR_CTRL_CLK_ENB              0
 
-#define SPEAR1340_PERIP3_CLK_ENB               (VA_MISC_BASE + 0x314)
+#define SPEAR1340_PERIP3_CLK_ENB               (misc_base + 0x314)
        #define SPEAR1340_PLGPIO_CLK_ENB                18
        #define SPEAR1340_VIDEO_DEC_CLK_ENB             16
        #define SPEAR1340_VIDEO_ENC_CLK_ENB             15
@@ -441,7 +440,7 @@ static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk",
 static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco2div2_clk",
        "pll2_clk", };
 
-void __init spear1340_clk_init(void)
+void __init spear1340_clk_init(void __iomem *misc_base)
 {
        struct clk *clk, *clk1;