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ENGR00277382-1 [MX6SL] Ensure that PLL1 and PLL2 are always enabled.
authorRanjani Vaidyanathan <ra5478@freescale.com>
Tue, 27 Aug 2013 22:57:55 +0000 (17:57 -0500)
committerLothar Waßmann <LW@KARO-electronics.de>
Wed, 20 Aug 2014 08:06:28 +0000 (10:06 +0200)
commit0fb71892fe5b67405eefc19d9405f718f7747802
tree13db9f174feb596030e992ad4f7759a5f91605e1tree | snapshot
parent6cd9012a1a5f9ced512a8dfb8c588b479b7e98f2commit | diff
ENGR00277382-1 [MX6SL] Ensure that PLL1 and PLL2 are always enabled.

Need to ensure that PLL1 and PLL2 have the enabled bit set even when
the PLL is powered down and disabled.

1. Modifications to the ARM_PODF bits in the CCM require PLL1 to be enabled.
2. PLL2 will be set to bypass and enabled state (can be powered down) in low
power IDLE mode.

Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
arch/arm/mach-imx/clk-imx6q.c diff | blob | history
arch/arm/mach-imx/clk-imx6sl.c diff | blob | history
arch/arm/mach-imx/clk-pllv3.c diff | blob | history
arch/arm/mach-imx/clk.h diff | blob | history
Linux kernel for KaRo TX COM modules