#define PTR(name)               \
.##name: .word  name

 
 
 

                              

        .file   "hal_initio.S"


#include <cyg/hal/hal_triton270.h>        // Platform specific hardware definitions




        .code   32
                       
        .global __hal_initio
__hal_initio:


	b 1924f

pin_state_table:

	.equ GPIO_DIR_INPUT, 0
	.equ GPIO_DIR_OUTPUT, 1
	.equ GPIO_AF0,	0
	.equ GPIO_AF1,	1
	.equ GPIO_AF2,	2
	.equ GPIO_AF3,	3
	.equ GPIO_LOW,	0
	.equ GPIO_HIGH,	1
	.equ GPIO_REDGE, 0x80
	.equ GPIO_FEDGE, 0x40
	.equ GPIO_NOEDGE, 0
	
	.balign 4

/*GPIO  0 */		.byte    0, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0
/*GPIO  1 */		.byte	 1, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0
/*GPIO  2 */		.byte	 2, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0
/*GPIO  3 */		.byte	 3, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0
/*GPIO  4 */		.byte	 4, GPIO_DIR_INPUT, 	GPIO_NOEDGE	| GPIO_LOW, 	GPIO_AF0
/*GPIO  5 */		.byte	 5, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0
/*GPIO  6 */		.byte	 6, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0
/*GPIO  7 */		.byte	 7, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0
/*GPIO  8 */		.byte	 8, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0
/*GPIO  9 */		.byte	 9, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0
/*GPIO 10 */		.byte	10, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_HIGH, 	GPIO_AF0		/* ETN Reset */
/*GPIO 11 */		.byte	11, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0
/*GPIO 12 */		.byte	12, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0
/*GPIO 13 */		.byte	13, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0
/*GPIO 14 */		.byte	14, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0		/* Backlight enable */
/*GPIO 15 */		.byte	15, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_HIGH, 	GPIO_AF1		/* PCE1# */
/*GPIO 16 */		.byte	16, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0
/*GPIO 17 */		.byte	17, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0
/*GPIO 18 */		.byte	18, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF1		/* RDY pin */
/*GPIO 19 */		.byte	19, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0
/*GPIO 20 */		.byte	20, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0
/*GPIO 21 */		.byte	21, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_HIGH, 	GPIO_AF0		/* USB pull up */
/*GPIO 22 */		.byte	22, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0
/*GPIO 23 */		.byte	23, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0
/*GPIO 24 */		.byte	24, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0
/*GPIO 25 */		.byte	25, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0
/*GPIO 26 */		.byte	26, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0
/*GPIO 27 */		.byte	27, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0
/*GPIO 28 */		.byte	28, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF1		/* AC97_BITCLK	*/
/*GPIO 29 */		.byte	29, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF1		/* AC97_SDATA_IN0 */
/*GPIO 30 */		.byte	30, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF2		/* AC97_SDATA_OUT */
/*GPIO 31 */		.byte	31, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF2		/* AC97_SYNC */


/*GPIO 32 */		.byte   32, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF2		/* MMCLK */
/*GPIO 33 */		.byte	33, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_HIGH, 	GPIO_AF2		/* CS5# -> CSETN# */
/*GPIO 34 */		.byte	34, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF1		/* FFRxD */
/*GPIO 35 */		.byte	35, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF1		/* FFCTS */
/*GPIO 36 */		.byte	36, GPIO_DIR_INPUT, 	GPIO_NOEDGE	| GPIO_LOW, 	GPIO_AF1		/* FFDCD */
/*GPIO 37 */		.byte	37, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF1		/* FFDSR */
/*GPIO 38 */		.byte	38, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF1		/* FFRI */
/*GPIO 39 */		.byte	39, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_HIGH, 	GPIO_AF2		/* FFTxD */
/*GPIO 40 */		.byte	40, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_HIGH, 	GPIO_AF2		/* FFDTR */
/*GPIO 41 */		.byte	41, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_HIGH, 	GPIO_AF2		/* FFRTS */
/*GPIO 42 */		.byte	42, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF1		/* BTRxD */
/*GPIO 43 */		.byte	43, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_HIGH, 	GPIO_AF2		/* BTTxD */
/*GPIO 44 */		.byte	44, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF1		/* BTCTS */
/*GPIO 45 */		.byte	45, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_HIGH, 	GPIO_AF2		/* BTRTS */
/*GPIO 46 */		.byte	46, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF2		/* STDRxD */
/*GPIO 47 */		.byte	47, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_HIGH, 	GPIO_AF1		/* STDTxD */
/*GPIO 48 */		.byte	48, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_HIGH, 	GPIO_AF2		/* POE# */
/*GPIO 49 */		.byte	49, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_HIGH, 	GPIO_AF2		/* PWE# */
/*GPIO 50 */		.byte	50, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_HIGH, 	GPIO_AF2		/* PIOR# */
/*GPIO 51 */		.byte	51, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_HIGH, 	GPIO_AF2		/* PIOW# */
/*GPIO 52 */		.byte	52, GPIO_DIR_INPUT, 	GPIO_REDGE  | GPIO_LOW, 	GPIO_AF0		/* ETNINT */
/*GPIO 53 */		.byte	53, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_HIGH, 	GPIO_AF0		/* MMC-Card CD# */
/*GPIO 54 */		.byte	54, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_HIGH, 	GPIO_AF0		/* MMC-Card WP# */
/*GPIO 55 */		.byte	55, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_HIGH, 	GPIO_AF2		/* PREG# */
/*GPIO 56 */		.byte	56, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF1		/* PWAIT */
/*GPIO 57 */		.byte	57, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF1		/* IOS16 */
/*GPIO 58 */		.byte	58, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF2		/* LDD0 */
/*GPIO 59 */		.byte	59, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF2		/* LDD1 */
/*GPIO 60 */		.byte	60, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF2		/* LDD2 */
/*GPIO 61 */		.byte	61, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF2		/* LDD3 */
/*GPIO 62 */		.byte	62, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF2		/* LDD4 */
/*GPIO 63 */		.byte	63, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF2		/* LDD5 */


/*GPIO 64 */		.byte   64, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF2		/* LDD6 */
/*GPIO 65 */		.byte	65, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF2		/* LDD7 */
/*GPIO 66 */		.byte	66, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF2		/* LDD8 */
/*GPIO 67 */		.byte	67, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF2		/* LDD9 */
/*GPIO 68 */		.byte	68, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE	| GPIO_LOW, 	GPIO_AF2		/* LDD10 */
/*GPIO 69 */		.byte	69, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF2		/* LDD11 */
/*GPIO 70 */		.byte	70, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF2		/* LDD12 */
/*GPIO 71 */		.byte	71, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF2		/* LDD13 */
/*GPIO 72 */		.byte	72, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF2		/* LDD14 */
/*GPIO 73 */		.byte	73, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF2		/* LDD15 */
/*GPIO 74 */		.byte	74, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF2		/* FCLK */
/*GPIO 75 */		.byte	75, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF2		/* LCLK */
/*GPIO 76 */		.byte	76, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF2		/* PCLK */
/*GPIO 77 */		.byte	77, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF2		/* LCD_DEN */
/*GPIO 78 */		.byte	78, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_HIGH, 	GPIO_AF1	/* PCE2# */
/*GPIO 79 */		.byte	79, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF1	/* PSKTSEL */
/*GPIO 80 */		.byte	80, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_HIGH, 	GPIO_AF0	/* Display enable or CS*/
/*GPIO 81 */		.byte	81, GPIO_DIR_INPUT, 	GPIO_REDGE  | GPIO_LOW, 	GPIO_AF0	/*CF IRQ */
/*GPIO 82 */		.byte	82, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0	/*CF Card Detect# */
/*GPIO 83 */		.byte	83, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_HIGH, 	GPIO_AF0	/*CF RESET */
/*GPIO 84 */		.byte	84, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0	/*CF BVD2# */
/*GPIO 85 */		.byte	85, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0	/*CF BVD1# */
/*GPIO 86 */		.byte	86, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF2	/* LDD16 */
/*GPIO 87 */		.byte	87, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF2	/* LDD17 */
/*GPIO 88 */		.byte	88, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF1 	/* USBHPWR1 USB Host power Status*/
/*GPIO 89 */		.byte	89, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_HIGH, 	GPIO_AF2	/* USBHPEN1 USB Host power Enable (set to off) */
/*GPIO 90 */		.byte	90, GPIO_DIR_INPUT, 	GPIO_REDGE  | GPIO_LOW, 	GPIO_AF0	/* UCB1400 IRQ */
/*GPIO 91 */		.byte	91, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0
/*GPIO 92 */		.byte	92, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF1	/* MMDAT0 */
/*GPIO 93 */		.byte	93, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0
/*GPIO 94 */		.byte	94, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0
/*GPIO 95 */		.byte	95, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0



/*GPIO 96 */		.byte   96, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0
/*GPIO 97 */		.byte	97, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0
/*GPIO 98 */		.byte	98, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0
/*GPIO 99 */		.byte	99, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0
/*GPIO 100 */		.byte  100, GPIO_DIR_INPUT, 	GPIO_NOEDGE	| GPIO_LOW, 	GPIO_AF0
/*GPIO 101 */		.byte  101, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0
/*GPIO 102 */		.byte  102, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0
/*GPIO 103 */		.byte  103, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0
/*GPIO 104 */		.byte  104, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0
/*GPIO 105 */		.byte  105, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0
/*GPIO 106 */		.byte  106, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0
/*GPIO 107 */		.byte  107, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0
/*GPIO 108 */		.byte  108, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0
/*GPIO 109 */		.byte  109, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF1	/* MMDAT1 */
/*GPIO 110 */		.byte  110, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF1	/* MMDAT2 */
/*GPIO 111 */		.byte  111, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF1	/* MMDAT3 */
/*GPIO 112 */		.byte  112, GPIO_DIR_INPUT, 	GPIO_NOEDGE	| GPIO_LOW, 	GPIO_AF1	/* MMCMD  */
/*GPIO 113 */		.byte  113, GPIO_DIR_OUTPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF2	/* AC97_RESET# */
/*GPIO 114 */		.byte  114, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0
/*GPIO 115 */		.byte  115, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0
/*GPIO 116 */		.byte  116, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0
/*GPIO 117 */		.byte  117, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0
/*GPIO 118 */		.byte  118, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0
/*GPIO 119 */		.byte  119, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0
/*GPIO 120 */		.byte  120, GPIO_DIR_INPUT, 	GPIO_NOEDGE | GPIO_LOW, 	GPIO_AF0
/*GPIO 121 */		.byte  121, 0, 					0, 			0
/*GPIO 122 */		.byte  122, 0, 					0, 			0
/*GPIO 123 */		.byte  123, 0, 					0, 			0
/*GPIO 124 */		.byte  124, 0, 					0, 			0
/*GPIO 125 */		.byte  125, 0, 					0, 			0
/*GPIO 126 */		.byte  126, 0, 					0, 			0
/*GPIO 127 */		.byte  127, 0, 					0, 			0
















	1924:
	





	
	
	//	must set the GPIOs up before any chip selects will work
	
	

	//GPCRa = 0xffffffff put a 0 on any of the GPIOs (0=unchanged, 1=drive 0)
	// reset all first
	ldr		r0,	=GPCRa
	ldr		r1,	=0xffffffff
	str		r1, [r0]
	//GPCRb = 0xffffffff
	ldr		r0,	=GPCRb
	ldr		r1,	=0xffffffff
	str		r1, [r0]
	//GPCRc = 0xffffffff
	ldr		r0,	=GPCRc
	ldr		r1,	=0xffffffff
	str		r1, [r0]
	//GPCRd = 0xffffffff
	ldr		r0,	=GPCRd
	ldr		r1,	=0xffffffff
	str		r1, [r0]

		
	
//  *************************************************************************************
//                   extract value for Output Set Register GPSRa from table
//  *************************************************************************************	
	ldr r0, =pin_state_table
	mov r1, #1						// mask register
	mov r2, #0						// this is the register where the value is composed
	
_exGPSRa0:
	ldr r3, [r0], #4				// load table entry, increase pointer
	ands r3, r3, #0x00010000
	beq _exGPSRa1					// ZERO flag is set
	orr r2, r2, r1					// OR mask bit to value
_exGPSRa1:
	mov r1, r1, ASL #1				// shift mask bit
	cmp r1, #0
	bne _exGPSRa0
	
	ldr r0, =GPSRa
	str r2, [r0]
		
	
//  *************************************************************************************
//                   extract value for Output Set Register GPSRb from table
//  *************************************************************************************	
	ldr r0, =pin_state_table
	add r0, r0, #128				// use second third of table
	mov r1, #1						// mask register
	mov r2, #0						// this is the register where the value is composed
	
_exGPSRb0:
	ldr r3, [r0], #4				// load table entry, increase pointer
	ands r3, r3, #0x00010000
	beq _exGPSRb1					// ZERO flag is set
	orr r2, r2, r1					// OR mask bit to value
_exGPSRb1:
	mov r1, r1, ASL #1				// shift mask bit
	cmp r1, #0
	bne _exGPSRb0
	
	ldr r0, =GPSRb
	str r2, [r0]
		


//  *************************************************************************************
//                   extract value for Output Set Register GPSRc from table
//  *************************************************************************************	
	ldr r0, =pin_state_table
	add r0, r0, #256				// use last third of table
	mov r1, #1						// mask register
	mov r2, #0						// this is the register where the value is composed
	
_exGPSRc0:
	ldr r3, [r0], #4				// load table entry, increase pointer
	ands r3, r3, #0x00010000
	beq _exGPSRc1					// ZERO flag is set
	orr r2, r2, r1					// OR mask bit to value
_exGPSRc1:
	mov r1, r1, ASL #1				// shift mask bit
	cmp r1, #0
	bne _exGPSRc0
	
	ldr r0, =GPSRc
	str r2, [r0]
		



//  *************************************************************************************
//                   extract value for Output Set Register GPSRd from table
//  *************************************************************************************	
	ldr r0, =pin_state_table
	add r0, r0, #384				// use last quarter of table
	mov r1, #1						// mask register
	mov r2, #0						// this is the register where the value is composed
	
_exGPSRd0:
	ldr r3, [r0], #4				// load table entry, increase pointer
	ands r3, r3, #0x00010000
	beq _exGPSRd1					// ZERO flag is set
	orr r2, r2, r1					// OR mask bit to value
_exGPSRd1:
	mov r1, r1, ASL #1				// shift mask bit
	cmp r1, #0
	bne _exGPSRd0
	
	ldr r0, =GPSRd
	str r2, [r0]
		








//  *************************************************************************************
//                   extract value for Direction Register GPDRa from table
//  *************************************************************************************	
	ldr r0, =pin_state_table
	mov r1, #1						// mask register
	mov r2, #0						// this is the register where the value is composed
	
_exGPDRa0:
	ldr r3, [r0], #4				// load table entry, increase pointer
	ands r3, r3, #0x00000100
	beq _exGPDRa1					// ZERO flag is set
	orr r2, r2, r1					// OR mask bit to value
_exGPDRa1:
	mov r1, r1, ASL #1				// shift mask bit
	cmp r1, #0
	bne _exGPDRa0
	
	ldr r0, =GPDRa
	ldr r5, =0x1e4
	bic r2, r2, r5					// reserved bits
	str r2, [r0]








		
	
//  *************************************************************************************
//                   extract value for Direction Register GPDRb from table
//  *************************************************************************************	
	ldr r0, =pin_state_table
	add r0, r0, #128				// use second quarter of table
	mov r1, #1						// mask register
	mov r2, #0						// this is the register where the value is composed
	
_exGPDRb0:
	ldr r3, [r0], #4				// load table entry, increase pointer
	ands r3, r3, #0x00000100
	beq _exGPDRb1					// ZERO flag is set
	orr r2, r2, r1					// OR mask bit to value
_exGPDRb1:
	mov r1, r1, ASL #1				// shift mask bit
	cmp r1, #0
	bne _exGPDRb0
	
	ldr r0, =GPDRb
	str r2, [r0]
		


//  *************************************************************************************
//                   extract value for Direction Register GPDRc from table
//  *************************************************************************************	
	ldr r0, =pin_state_table
	add r0, r0, #256				// use third quarter of table
	mov r1, #1						// mask register
	mov r2, #0						// this is the register where the value is composed
	
_exGPDRc0:
	ldr r3, [r0], #4				// load table entry, increase pointer
	ands r3, r3, #0x00000100
	beq _exGPDRc1					// ZERO flag is set
	orr r2, r2, r1					// OR mask bit to value
_exGPDRc1:
	mov r1, r1, ASL #1				// shift mask bit
	cmp r1, #0
	bne _exGPDRc0
	
	ldr r0, =GPDRc
	str r2, [r0]
		



//  *************************************************************************************
//                   extract value for Direction Register GPDRd from table
//  *************************************************************************************	
	ldr r0, =pin_state_table
	add r0, r0, #384				// use last quarter of table
	mov r1, #1						// mask register
	mov r2, #0						// this is the register where the value is composed
	
_exGPDRd0:
	ldr r3, [r0], #4				// load table entry, increase pointer
	ands r3, r3, #0x00000100
	beq _exGPDRd1					// ZERO flag is set
	orr r2, r2, r1					// OR mask bit to value
_exGPDRd1:
	mov r1, r1, ASL #1				// shift mask bit
	cmp r1, #0
	bne _exGPDRd0
	
	ldr r0, =GPDRd
	str r2, [r0]
		












//  *************************************************************************************
//                   extract value for Alternate Function Register GAFR0a from table
//  *************************************************************************************	
	ldr r0, =pin_state_table
	mov r1, #1						// mask register
	mov r2, #0						// this is the register where the value is composed
	
_exGAFR0a0:
	ldr r3, [r0], #4				// load table entry, increase pointer
	ands r4, r3, #0x01000000
	beq _exGAFR0a1					// ZERO flag is set
	orr r2, r2, r1					// OR mask bit to value
_exGAFR0a1:
	mov r1, r1, ASL #1				// shift mask bit
	ands r4, r3, #0x02000000
	beq _exGAFR0a2					// ZERO flag is set
	orr r2, r2, r1					// OR mask bit to value
_exGAFR0a2:
	mov r1, r1, ASL #1				// shift mask bit
	cmp r1, #0
	bne _exGAFR0a0
	
	ldr r0, =GAFR0a
	str r2, [r0]
		

//  *************************************************************************************
//                   extract value for Alternate Function Register GAFR1a from table
//  *************************************************************************************	
	ldr r0, =pin_state_table
	add r0, r0, #64
	mov r1, #1						// mask register
	mov r2, #0						// this is the register where the value is composed
	
_exGAFR1a0:
	ldr r3, [r0], #4				// load table entry, increase pointer
	ands r4, r3, #0x01000000
	beq _exGAFR1a1					// ZERO flag is set
	orr r2, r2, r1					// OR mask bit to value
_exGAFR1a1:
	mov r1, r1, ASL #1				// shift mask bit
	ands r4, r3, #0x02000000
	beq _exGAFR1a2					// ZERO flag is set
	orr r2, r2, r1					// OR mask bit to value
_exGAFR1a2:
	mov r1, r1, ASL #1				// shift mask bit
	cmp r1, #0
	bne _exGAFR1a0
	
	ldr r0, =GAFR1a
	str r2, [r0]
		




//  *************************************************************************************
//                   extract value for Alternate Function Register GAFR0b from table
//  *************************************************************************************	
	ldr r0, =pin_state_table
	add r0, r0, #128
	mov r1, #1						// mask register
	mov r2, #0						// this is the register where the value is composed
	
_exGAFR0b0:
	ldr r3, [r0], #4				// load table entry, increase pointer
	ands r4, r3, #0x01000000
	beq _exGAFR0b1					// ZERO flag is set
	orr r2, r2, r1					// OR mask bit to value
_exGAFR0b1:
	mov r1, r1, ASL #1				// shift mask bit
	ands r4, r3, #0x02000000
	beq _exGAFR0b2					// ZERO flag is set
	orr r2, r2, r1					// OR mask bit to value
_exGAFR0b2:
	mov r1, r1, ASL #1				// shift mask bit
	cmp r1, #0
	bne _exGAFR0b0
	
	ldr r0, =GAFR0b
	str r2, [r0]
		

//  *************************************************************************************
//                   extract value for Alternate Function Register GAFR1b from table
//  *************************************************************************************	
	ldr r0, =pin_state_table
	add r0, r0, #192
	mov r1, #1						// mask register
	mov r2, #0						// this is the register where the value is composed
	
_exGAFR1b0:
	ldr r3, [r0], #4				// load table entry, increase pointer
	ands r4, r3, #0x01000000
	beq _exGAFR1b1					// ZERO flag is set
	orr r2, r2, r1					// OR mask bit to value
_exGAFR1b1:
	mov r1, r1, ASL #1				// shift mask bit
	ands r4, r3, #0x02000000
	beq _exGAFR1b2					// ZERO flag is set
	orr r2, r2, r1					// OR mask bit to value
_exGAFR1b2:
	mov r1, r1, ASL #1				// shift mask bit
	cmp r1, #0
	bne _exGAFR1b0
	
	ldr r0, =GAFR1b
	str r2, [r0]
		



//  *************************************************************************************
//                   extract value for Alternate Function Register GAFR0c from table
//  *************************************************************************************	
	ldr r0, =pin_state_table
	add r0, r0, #256
	mov r1, #1						// mask register
	mov r2, #0						// this is the register where the value is composed
	
_exGAFR0c0:
	ldr r3, [r0], #4				// load table entry, increase pointer
	ands r4, r3, #0x01000000
	beq _exGAFR0c1					// ZERO flag is set
	orr r2, r2, r1					// OR mask bit to value
_exGAFR0c1:
	mov r1, r1, ASL #1				// shift mask bit
	ands r4, r3, #0x02000000
	beq _exGAFR0c2					// ZERO flag is set
	orr r2, r2, r1					// OR mask bit to value
_exGAFR0c2:
	mov r1, r1, ASL #1				// shift mask bit
	cmp r1, #0
	bne _exGAFR0c0
	
	ldr r0, =GAFR0c
	str r2, [r0]
		

//  *************************************************************************************
//                   extract value for Alternate Function Register GAFR1c from table
//  *************************************************************************************	
	ldr r0, =pin_state_table
	add r0, r0, #320
	mov r1, #1						// mask register
	mov r2, #0						// this is the register where the value is composed
	
_exGAFR1c0:
	ldr r3, [r0], #4				// load table entry, increase pointer
	ands r4, r3, #0x01000000
	beq _exGAFR1c1					// ZERO flag is set
	orr r2, r2, r1					// OR mask bit to value
_exGAFR1c1:
	mov r1, r1, ASL #1				// shift mask bit
	ands r4, r3, #0x02000000
	beq _exGAFR1c2					// ZERO flag is set
	orr r2, r2, r1					// OR mask bit to value
_exGAFR1c2:
	mov r1, r1, ASL #1				// shift mask bit
	cmp r1, #0
	bne _exGAFR1c0
	
	ldr r0, =GAFR1c
	str r2, [r0]
		





//  *************************************************************************************
//                   extract value for Alternate Function Register GAFR0d from table
//  *************************************************************************************	
	ldr r0, =pin_state_table
	add r0, r0, #384
	mov r1, #1						// mask register
	mov r2, #0						// this is the register where the value is composed
	
_exGAFR0d0:
	ldr r3, [r0], #4				// load table entry, increase pointer
	ands r4, r3, #0x01000000
	beq _exGAFR0d1					// ZERO flag is set
	orr r2, r2, r1					// OR mask bit to value
_exGAFR0d1:
	mov r1, r1, ASL #1				// shift mask bit
	ands r4, r3, #0x02000000
	beq _exGAFR0d2					// ZERO flag is set
	orr r2, r2, r1					// OR mask bit to value
_exGAFR0d2:
	mov r1, r1, ASL #1				// shift mask bit
	cmp r1, #0
	bne _exGAFR0d0
	
	ldr r0, =GAFR0d
	str r2, [r0]
		

//  *************************************************************************************
//                   extract value for Alternate Function Register GAFR1d from table
//  *************************************************************************************	
	ldr r0, =pin_state_table
	add r0, r0, #448
	mov r1, #1						// mask register
	mov r2, #0						// this is the register where the value is composed
	
_exGAFR1d0:
	ldr r3, [r0], #4				// load table entry, increase pointer
	ands r4, r3, #0x01000000
	beq _exGAFR1d1					// ZERO flag is set
	orr r2, r2, r1					// OR mask bit to value
_exGAFR1d1:
	mov r1, r1, ASL #1				// shift mask bit
	ands r4, r3, #0x02000000
	beq _exGAFR1d2					// ZERO flag is set
	orr r2, r2, r1					// OR mask bit to value
_exGAFR1d2:
	mov r1, r1, ASL #1				// shift mask bit
	cmp r1, #0
	bne _exGAFR1d0
	
	ldr r0, =GAFR1d
	str r2, [r0]
		

























//  *************************************************************************************
//                   extract value for Rising Edge Register GRERa from table
//  *************************************************************************************	
	ldr r0, =pin_state_table
	mov r1, #1						// mask register
	mov r2, #0						// this is the register where the value is composed
	
_exGRERa0:
	ldr r3, [r0], #4				// load table entry, increase pointer
	ands r3, r3, #0x00800000
	beq _exGRERa1					// ZERO flag is set
	orr r2, r2, r1					// OR mask bit to value
_exGRERa1:
	mov r1, r1, ASL #1				// shift mask bit
	cmp r1, #0
	bne _exGRERa0
	
	ldr r0, =GRERa
	str r2, [r0]
		
	
//  *************************************************************************************
//                   extract value for Rising Edge Register GRERb from table
//  *************************************************************************************	
	ldr r0, =pin_state_table
	add r0, r0, #128				// use second third of table
	mov r1, #1						// mask register
	mov r2, #0						// this is the register where the value is composed
	
_exGRERb0:
	ldr r3, [r0], #4				// load table entry, increase pointer
	ands r3, r3, #0x00800000
	beq _exGRERb1					// ZERO flag is set
	orr r2, r2, r1					// OR mask bit to value
_exGRERb1:
	mov r1, r1, ASL #1				// shift mask bit
	cmp r1, #0
	bne _exGRERb0
	
	ldr r0, =GRERb
	str r2, [r0]
		



//  *************************************************************************************
//                   extract value for Rising Edge Register GRERc from table
//  *************************************************************************************	
	ldr r0, =pin_state_table
	add r0, r0, #256				// use last third of table
	mov r1, #1						// mask register
	mov r2, #0						// this is the register where the value is composed
	
_exGRERc0:
	ldr r3, [r0], #4				// load table entry, increase pointer
	ands r3, r3, #0x00800000
	beq _exGRERc1					// ZERO flag is set
	orr r2, r2, r1					// OR mask bit to value
_exGRERc1:
	mov r1, r1, ASL #1				// shift mask bit
	cmp r1, #0
	bne _exGRERc0
	
	ldr r0, =GRERc
	str r2, [r0]
		
		
//  *************************************************************************************
//                   extract value for Rising Edge Register GRERd from table
//  *************************************************************************************	
	ldr r0, =pin_state_table
	add r0, r0, #384				// use last third of table
	mov r1, #1						// mask register
	mov r2, #0						// this is the register where the value is composed
	
_exGRERd0:
	ldr r3, [r0], #4				// load table entry, increase pointer
	ands r3, r3, #0x00800000
	beq _exGRERd1					// ZERO flag is set
	orr r2, r2, r1					// OR mask bit to value
_exGRERd1:
	mov r1, r1, ASL #1				// shift mask bit
	cmp r1, #0
	bne _exGRERd0
	
	ldr r0, =GRERd
	str r2, [r0]
		
		




//  *************************************************************************************
//                   extract value for Falling Edge Register GFERa from table
//  *************************************************************************************	
	ldr r0, =pin_state_table
	mov r1, #1						// mask register
	mov r2, #0						// this is the register where the value is composed
	
_exGFERa0:
	ldr r3, [r0], #4				// load table entry, increase pointer
	ands r3, r3, #0x00400000
	beq _exGFERa1					// ZERO flag is set
	orr r2, r2, r1					// OR mask bit to value
_exGFERa1:
	mov r1, r1, ASL #1				// shift mask bit
	cmp r1, #0
	bne _exGFERa0
	
	ldr r0, =GFERa
	str r2, [r0]
		
	
//  *************************************************************************************
//                   extract value for Falling Edge Register GFERb from table
//  *************************************************************************************	
	ldr r0, =pin_state_table
	add r0, r0, #128				// use second third of table
	mov r1, #1						// mask register
	mov r2, #0						// this is the register where the value is composed
	
_exGFERb0:
	ldr r3, [r0], #4				// load table entry, increase pointer
	ands r3, r3, #0x00400000
	beq _exGFERb1					// ZERO flag is set
	orr r2, r2, r1					// OR mask bit to value
_exGFERb1:
	mov r1, r1, ASL #1				// shift mask bit
	cmp r1, #0
	bne _exGFERb0
	
	ldr r0, =GFERb
	str r2, [r0]
		


//  *************************************************************************************
//                   extract value for Falling Edge Register GFERc from table
//  *************************************************************************************	
	ldr r0, =pin_state_table
	add r0, r0, #256				// use last third of table
	mov r1, #1						// mask register
	mov r2, #0						// this is the register where the value is composed
	
_exGFERc0:
	ldr r3, [r0], #4				// load table entry, increase pointer
	ands r3, r3, #0x00400000
	beq _exGFERc1					// ZERO flag is set
	orr r2, r2, r1					// OR mask bit to value
_exGFERc1:
	mov r1, r1, ASL #1				// shift mask bit
	cmp r1, #0
	bne _exGFERc0
	
	ldr r0, =GFERc
	str r2, [r0]


//  *************************************************************************************
//                   extract value for Falling Edge Register GFERd from table
//  *************************************************************************************	
	ldr r0, =pin_state_table
	add r0, r0, #384				// use last quarter of table
	mov r1, #1						// mask register
	mov r2, #0						// this is the register where the value is composed
	
_exGFERd0:
	ldr r3, [r0], #4				// load table entry, increase pointer
	ands r3, r3, #0x00400000
	beq _exGFERd1					// ZERO flag is set
	orr r2, r2, r1					// OR mask bit to value
_exGFERd1:
	mov r1, r1, ASL #1				// shift mask bit
	cmp r1, #0
	bne _exGFERd0
	
	ldr r0, =GFERd
	str r2, [r0]

	




	mov r15, r14					// return
 
       
        
 
 

// --------------------------------------------------------------------------
//  end of hal_initio.S