};
# <
+# MXC FEC MII Gasket for RMII mode
+# This option enables the use of the MII Gasket for
+# RMII mode found in i.MX25 and i.MX53 processors.
+#
+cdl_option CYGOPT_HAL_ARM_MXC_FEC_MIIGSK {
+ # This option is not active
+ # ActiveIf constraint: CYGPKG_HAL_ARM_MX25 || CYGPKG_HAL_ARM_MX53
+ # CYGPKG_HAL_ARM_MX25 (unknown) == 0
+ # CYGPKG_HAL_ARM_MX53 (unknown) == 0
+ # --> 0
+
+ # Flavor: bool
+ # No user value, uncomment the following line to provide one.
+ # user_value 1
+ # value_source default
+ # Default value: 1
+};
+
# <
# Ethernet transceiver (PHY) support
# API for ethernet PHY devices
#
cdl_option CYGHWR_HAL_ARM_DUMP_EXCEPTIONS {
# Flavor: bool
- user_value 1
- # value_source user
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
# Default value: 0
# Requires: !CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
# CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
# user_value 0x08000000
# value_source default
# Default value: 0x08000000
- # Legal values: 0x08000000 0x04000000
+ # Legal values: 0x10000000 0x08000000 0x04000000
+};
+
+# SDRAM clock
+# This option specifies the SDRAM clock im MHz of the TX51 module.
+#
+cdl_option CYGNUM_HAL_ARM_TX51_SDRAM_CLK {
+ # Flavor: data
+ # No user value, uncomment the following line to provide one.
+ # user_value 166
+ # value_source default
+ # Default value: 166
+ # Legal values: 166 200
};
# Enable low level debugging with LED
# Flavor: bool
# No user value, uncomment the following line to provide one.
# user_value 1
- # value_source default
+ # The inferred value should not be edited directly.
+ inferred_value 0
+ # value_source inferred
# Default value: 1
};