- /* iomux reg offset, func, gpgrp, */
- /* gpiofn, gpshift, */
- { IOMUXC_SW_MUX_CTL_PAD_NANDF_CS3, 0x12, 0x13, 3, 19, }, /* MDC */
- { IOMUXC_SW_MUX_CTL_PAD_EIM_EB2, 0x13, 0x11, 2, 22, }, /* MDIO */
- { IOMUXC_SW_MUX_CTL_PAD_NANDF_RB3, 0x11, 0x13, 3, 11, }, /* RXC */
- { IOMUXC_SW_MUX_CTL_PAD_NANDF_D11, 0x12, 0x13, 3, 29, }, /* RDV */
- { IOMUXC_SW_MUX_CTL_PAD_NANDF_D9, 0x12, 0x13, 3, 31, }, /* RXD0 */
- { IOMUXC_SW_MUX_CTL_PAD_EIM_EB3, 0x13, 0x11, 2, 23, }, /* RXD1 */
- { IOMUXC_SW_MUX_CTL_PAD_EIM_CS2, 0x13, 0x11, 2, 27, }, /* RXD2 */
- { IOMUXC_SW_MUX_CTL_PAD_EIM_CS3, 0x13, 0x11, 2, 28, }, /* RXD3 */
- { IOMUXC_SW_MUX_CTL_PAD_EIM_CS4, 0x13, 0x11, 2, 29, }, /* RX_ER */
- { IOMUXC_SW_MUX_CTL_PAD_NANDF_RDY_INT, 0x11, 0x13, 3, 24, }, /* TXC */
- { IOMUXC_SW_MUX_CTL_PAD_NANDF_CS7, 0x11, 0x13, 3, 23, }, /* TXE */
- { IOMUXC_SW_MUX_CTL_PAD_NANDF_D8, 0x12, 0x13, 4, 0, }, /* TXD0 */
- { IOMUXC_SW_MUX_CTL_PAD_NANDF_CS4, 0x12, 0x13, 3, 20, }, /* TXD1 */
- { IOMUXC_SW_MUX_CTL_PAD_NANDF_CS5, 0x12, 0x13, 3, 21, }, /* TXD2 */
- { IOMUXC_SW_MUX_CTL_PAD_NANDF_CS6, 0x12, 0x13, 3, 22, }, /* TXD3 */
- { IOMUXC_SW_MUX_CTL_PAD_NANDF_RB2, 0x11, 0x13, 3, 10, }, /* COL */
- { IOMUXC_SW_MUX_CTL_PAD_EIM_CS5, 0x13, 0x11, 2, 30, }, /* CRS */
- { IOMUXC_SW_MUX_CTL_PAD_NANDF_CS2, 0x13, 0x13, 3, 18, }, /* TX_ER */
-};
-
-static struct tx51_gpio_setup tx51_fec_pwr_pins[] = {
- { IOMUXC_SW_MUX_CTL_PAD_EIM_A20, 0x11, 0x11, 2, 14, }, /* PHY reset */
- { IOMUXC_SW_MUX_CTL_PAD_GPIO1_3, 0x10, 0x10, 1, 3, }, /* PHY power enable */
+ /* iomux reg offset, func, gpgrp, in/out */
+ /* gpiofn, gpshft,level */
+ { IOMUXC_SW_MUX_CTL_PAD_EIM_A20, 0x11, 0x11, 2, 14, 1, 0, }, /* PHY reset */
+ { IOMUXC_SW_MUX_CTL_PAD_GPIO1_3, 0x10, 0x10, 1, 3, 1, 1, }, /* PHY power enable */
+ { IOMUXC_SW_MUX_CTL_PAD_NANDF_CS3, 0x02, 0x13, 3, 19, 1, 0, }, /* MDC */
+ { IOMUXC_SW_MUX_CTL_PAD_EIM_EB2, 0x03, 0x11, 2, 22, 1, 0, }, /* MDIO */
+ { IOMUXC_SW_MUX_CTL_PAD_NANDF_RB3, 0x01, 0x13, 3, 11, 0, }, /* RX_CLK */
+ { IOMUXC_SW_MUX_CTL_PAD_NANDF_D11, 0x02, 0x13, 3, 29, 0, }, /* RX_DV */
+ { IOMUXC_SW_MUX_CTL_PAD_NANDF_D9, 0x02, 0x13, 3, 31, 1, 1, }, /* RXD0/Mode0 */
+ { IOMUXC_SW_MUX_CTL_PAD_EIM_EB3, 0x03, 0x11, 2, 23, 1, 1, }, /* RXD1/Mode1 */
+ { IOMUXC_SW_MUX_CTL_PAD_EIM_CS2, 0x03, 0x11, 2, 27, 1, 1, }, /* RXD2/Mode2 */
+ { IOMUXC_SW_MUX_CTL_PAD_EIM_CS3, 0x03, 0x11, 2, 28, 1, 1, }, /* RXD3/nINTSEL */
+ { IOMUXC_SW_MUX_CTL_PAD_EIM_CS4, 0x03, 0x11, 2, 29, 0, }, /* RX_ER/RXD4 */
+ { IOMUXC_SW_MUX_CTL_PAD_NANDF_RDY_INT, 0x01, 0x13, 3, 24, 0, }, /* TX_CLK */
+ { IOMUXC_SW_MUX_CTL_PAD_NANDF_CS7, 0x01, 0x13, 3, 23, 1, 0, }, /* TX_EN */
+ { IOMUXC_SW_MUX_CTL_PAD_NANDF_D8, 0x02, 0x13, 4, 0, 1, 0, }, /* TXD0 */
+ { IOMUXC_SW_MUX_CTL_PAD_NANDF_CS4, 0x02, 0x13, 3, 20, 1, 0, }, /* TXD1 */
+ { IOMUXC_SW_MUX_CTL_PAD_NANDF_CS5, 0x02, 0x13, 3, 21, 1, 0, }, /* TXD2 */
+ { IOMUXC_SW_MUX_CTL_PAD_NANDF_CS6, 0x02, 0x13, 3, 22, 1, 0, }, /* TXD3 */
+ { IOMUXC_SW_MUX_CTL_PAD_NANDF_RB2, 0x01, 0x13, 3, 10, 1, 0, }, /* COL/RMII/CRSDV */
+ { IOMUXC_SW_MUX_CTL_PAD_EIM_CS5, 0x03, 0x11, 2, 30, 1, 0, }, /* CRS */
+ { IOMUXC_SW_MUX_CTL_PAD_NANDF_CS2, 0x03, 0x13, 3, 18, 0, }, /* nINT/TX_ER/TXD4 */