ldr r0, UART1_UBMR_W
str r0, [r1, #0xa8] @ UBMR
-#if 0
-1:
-#if 0
- ldr r0, [r1, #0x94] @ USR1
- tst r0, #(1 << 4) @ AWAKE
- beq 1b
-#else
- ldr r0, [r1, #0x98] @ USR2
- tst r0, #(1 << 15) @ ADET
- beq 1b
-#endif
- mov r0, #'*'
- str r0, [r1, #0x40] @TXFIFO
-#if 0
- mov r2, #RAM_BANK1_BASE
- ldr r0, [r1, #0xa4] @ UBIR
- str r0, [r2], #4
- ldr r0, [r1, #0xa8] @ UBMR
- str r0, [r2], #4
-#endif
-#endif
.endm
.macro uart_putc,c
ldr r7, CCM_BASE_ADDR_W
ldr r1, [r7, #CLKCTL_RCSR]
/* BUS WIDTH setting */
- tst r1, #(1 << 24)// Freescale: 0x20000000
+ tst r1, #(1 << 24)
orrne r1, r1, #(1 << 14)
biceq r1, r1, #(1 << 14)
/* 4K PAGE */
- tst r1, #(1 << 27)// Freescale: 0x10000000
+ tst r1, #(1 << 27)
orrne r1, r1, #(1 << 9)
bne 1f
/* 2K PAGE */
bic r1, r1, #(1 << 9)
- tst r1, #(1 << 26)// Freescale: 0x08000000
+ tst r1, #(1 << 26)
orrne r1, r1, #(1 << 8) /* 2KB page size */
biceq r1, r1, #(1 << 8) /* 512B page size */
movne r2, #(64 >> 1) /* 64 bytes */
moveq r2, #8 /* 16 bytes */
b NAND_setup
1:
- tst r1, #(1 << 26)// Freescale: 0x08000000
+ tst r1, #(1 << 26)
bicne r3, r3, #1 /* Enable 8bit ECC mode */
movne r2, #109 /* 218 bytes */
moveq r2, #(128 >> 1) /* 128 bytes */
#define PLATFORM_VECTORS _platform_vectors
.macro _platform_vectors
+ .globl _KARO_MAGIC
+_KARO_MAGIC:
+ .ascii "KARO_CE6"
+ .globl _KARO_STRUCT_SIZE
+_KARO_STRUCT_SIZE:
+ .word 0 // reserve space structure length
+
+ .globl _KARO_CECFG_START
+_KARO_CECFG_START:
+ .rept 1024/4
+ .word 0 // reserve space for CE configuration
+ .endr
+
+ .globl _KARO_CECFG_END
+_KARO_CECFG_END:
.endm
//Internal Boot, from MMC/SD cards or NAND flash
CCM_CGR1_W: .word 0xFFFFFFFF
CCM_CGR2_W: .word 0x000FDFFF
CCM_BASE_ADDR_W: .word CCM_BASE_ADDR
-CCM_CCTL_VAL_W: .word 0x30030000
+CCM_CCTL_VAL_W: .word 0x20034000
/*-----------------------------------------------------------------------*/
/* end of hal_platform_setup.h */
#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */